intel/i440bx: Correct RAM init programming
Corrects MBSC/MBFS programming when initializing DRAM on boards with both 3 and 4 DIMM slots. Reformats comments to current coreboot standards. Drops some romcc "optimizations" no longer necessary. Boot tested on asus/p2b-ls, where it fixes a memory related hang after SeaBIOS resets the board with nothing to boot from. Change-Id: Ib8c21489338643e13f69bd58008d14733796d4d0 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/22687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Keith Hui
Martin Roth
parent
ea8de493ff
commit
a8380fcfd8
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@ -132,10 +132,10 @@ static const u8 register_values[] = {
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*
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* [7:6] Reserved
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* [5:5] Module Mode Configuration (MMCONFIG)
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* The combination of SDRAMPWR and this bit (which is set by an
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* The combination of SDRAMPWR and this bit (set by an
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* external strapping option) determine how CKE works.
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* SDRAMPWR MMCONFIG
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* 0 0 = 3 DIMM, CKE0[5:0] driven
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* 0 0 = 3 DIMM, CKE[5:0] driven
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* X 1 = 3 DIMM, CKE0 only
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* 1 0 = 4 DIMM, GCKE only
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* [4:3] DRAM Type (DT)
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@ -188,9 +188,6 @@ static const u8 register_values[] = {
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* you want to use the RAM area from 768 KB - 1 MB. If the PAM
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* registers are not set here appropriately, the RAM in that region
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* will not be accessible, thus a RAM check of it will also fail.
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*
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* TODO: This was set in sdram_set_spd_registers().
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* Test if it still works when set here.
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*/
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PAM0, 0x00, 0x30,
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PAM1, 0x00, 0x33,
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@ -215,7 +212,7 @@ static const u8 register_values[] = {
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* 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB)
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* 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB)
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*/
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/* Set the DRBs to zero for now, this will be fixed later. */
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/* DRBs will be set later. */
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DRB0, 0x00, 0x00,
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DRB1, 0x00, 0x00,
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DRB2, 0x00, 0x00,
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@ -304,7 +301,6 @@ static const u8 register_values[] = {
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#else
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SDRAMC + 0, 0x00, 0x00, /* The board has 3 DIMM slots. */
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#endif
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SDRAMC + 1, 0x00, 0x00,
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/* PGPOL - Paging Policy Register
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* 0x78 - 0x79
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@ -431,40 +427,44 @@ static void do_ram_command(u32 command)
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static void set_dram_buffer_strength(void)
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{
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/* To give some breathing room for romcc,
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* mbsc0 doubles as drb
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* mbsc1 doubles as drb1
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* mbfs0 doubles as i and reg
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/*
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* Program MBSC[39:0] and MBFS[23:0].
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*
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* The 440BX datasheet says buffer frequency is independent from bus
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* frequency and mismatch both ways are possible.
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*
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* MBSC[47:40] and MBFS[23] are reserved.
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*/
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uint8_t mbsc0,mbsc1,mbsc3,mbsc4,mbfs0,mbfs2,fsb;
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/* Tally how many rows between rows 0-3 and rows 4-7 are populated.
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unsigned int i, reg, drb;
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uint8_t mbsc0, mbfs0, mbfs1, mbfs2;
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uint16_t mbsc1, mbsc3;
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/*
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* Tally how many rows between rows 0-3 and rows 4-7 are populated.
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* This determines how to program MBFS and MBSC.
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*/
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uint8_t dimm03 = 0;
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uint8_t dimm47 = 0;
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mbsc0 = 0;
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for (mbfs0 = DRB0; mbfs0 <= DRB7; mbfs0++) {
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mbsc1 = pci_read_config8(NB, mbfs0);
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if (mbsc0 != mbsc1) {
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if (mbfs0 <= DRB3) {
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for (drb = 0, i = DRB0; i <= DRB7; i++) {
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reg = pci_read_config8(NB, i);
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if (drb != reg) {
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if (i <= DRB3)
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dimm03++;
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} else {
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else
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dimm47++;
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}
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mbsc0 = mbsc1;
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drb = reg;
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}
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}
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/* Algorithm bitmap for programming MBSC[39:0] and MBFS[23:0].
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if (IS_ENABLED(CONFIG_SDRAMPWR_4DIMM)) {
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/*
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* For a 4 DIMM board, based on ASUS P2B-LS mainboard.
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*
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* The 440BX datasheet says buffer frequency is independent from bus
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* frequency and mismatch both ways are possible. This is how it is
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* programmed in the ASUS P2B-LS mainboard.
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*
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* There are four main conditions to check when programming DRAM buffer
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* frequency and strength:
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* There are four main conditions to check when programming
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* DRAM buffer frequency and strength:
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*
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* a: >2 rows populated across DIMM0,1
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* b: >2 rows populated across DIMM2,3
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@ -474,17 +474,110 @@ static void set_dram_buffer_strength(void)
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* 6: NBXCFG[13] strapped as 66MHz
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*
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* CKE0/FENA ----------------------------------------------------------+
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* CKE1/GCKE -------------------[ MBFS ]------------------------+|
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* CKE1/GCKE ----------------------[ MBFS ]---------------------+|
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* DQMA/CASA[764320]# -------------[ 0 = 66MHz ]--------------------+||
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* DQMB1/CASB1# (Fixed for 66MHz) -[ 1 = 100MHz ]-------------------+|||
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* DQMB5/CASB5# (Fixed for 66MHz) ---------------------------------+||||
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* DQMA1/CASA1# (Fixed for 66MHz) --------------------------------+|||||
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* DQMA5/CASA5# (Fixed for 66MHz) -------------------------------+||||||
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* CSA[5:0]#,CSB[5:0]# ------------------------------------++++++|||||||
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* CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
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* MECC[7:0] #2/#1 ----------------------------------++|||||||||||||||||
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* MD[63:0] #2/#1 ---------------------------------++|||||||||||||||||||
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* MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
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* MAA[13:0],WEA#,SRASA#,SCASA# -----------------+||||||||||||||||||||||
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* Reserved ------------------------------------+|||||||||||||||||||||||
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* ||||||||||||||||||||||||
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* 3 32 21 10 0 * 2 21 10 0
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* 9876543210987654321098765432109876543210 * 321098765432109876543210
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* 10------------------------1010---------- a -1---------------11-----
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* 11------------------------1111---------- !a -0---------------00-----
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* --10--------------------------1010------ b --1----------------11---
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* --11--------------------------1111------ !b --0----------------00---
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* ----------------------------------1100-- c ----------------------1-
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* ----------------------------------1011-- !c ----------------------0-
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* ----1010101000000000000000------------00 1 ---11111111111111----1-0
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* ----000000000000000000000010101010----00 6 ---1111111111111100000-0
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* | | | | | | | | | | ||||||| | | | | | |
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* | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA
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* | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE
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* | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
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* | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1# (66MHz: 2x)
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* | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5# (66MHz: 2x)
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* | | | | | | | | | | ||||||| +----------- DQMA1/CASA1# (66MHz: 2x)
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* | | | | | | | | | | ||||||+------------- DQMA5/CASA5# (66MHz: 2x)
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* | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (1x)
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* | | | | | | | | | +--------------------- CSA6#/CKE2
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* | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
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* | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
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* | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
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* | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1
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* | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2
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* | | | +--------------------------------- MD[63:0] #1
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* | | +----------------------------------- MD[63:0] #2
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* | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
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* +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
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*/
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unsigned int fsb;
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mbsc0 = 0xa0;
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mbsc1 = 0x002a;
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mbfs1 = 0xff;
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mbfs2 = 0x1f;
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if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {
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fsb = 66;
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mbsc3 = 0xa000;
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mbfs0 = 0x80;
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} else {
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fsb = 100;
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mbsc3 = 0xaaa0;
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mbfs0 = 0x84;
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}
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if (dimm03 > 2) {
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mbfs2 |= 0x40;
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if (fsb == 100)
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mbfs0 |= 0x60;
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} else {
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mbsc3 |= 0xc000;
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if (fsb == 100)
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mbsc1 |= 0x003c;
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}
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if (dimm47 > 2) {
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mbfs2 |= 0x20;
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if (fsb == 100)
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mbfs0 |= 0x18;
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} else {
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mbsc3 |= 0x3000;
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if (fsb == 100) {
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mbsc1 |= 0x0003;
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mbsc0 |= 0xc0;
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}
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}
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if ((dimm03 + dimm47) > 4) {
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mbsc0 |= 0x30;
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mbfs0 |= 0x02;
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} else {
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mbsc0 |= 0x2c;
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}
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} else {
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/*
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* For a 3 DIMM board, based on ASUS P2B mainboard.
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*
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* There are two main conditions to check when programming DRAM buffer
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* frequency and strength:
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*
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* a: >2 rows populated across DIMM0,1
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* c: >4 rows populated across all DIMM slots
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*
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* CKE0 ---------------------------------------------------------------+
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* CKE1 ------------------------[ MBFS ]------------------------+|
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* DQMA/CASA[764320]# ----------[ 0 = 66MHz ]-----------------------+||
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* DQMB1/CASB1# ----------------[ 1 = 100MHz ]----------------------+|||
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* DQMB5/CASB5# ---------------------------------------------------+||||
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* DQMA1/CASA1# --------------------------------------------------+|||||
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* DQMA5/CASA5# -------------------------------------------------+||||||
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* CSA0-5#,CSB0-5# ----------------------------------------++++++|||||||
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* CSA6#/CKE2# -------------------------------------------+|||||||||||||
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* CSB6#/CKE4# ------------------------------------------+||||||||||||||
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* CSA7#/CKE3# -----------------------------------------+|||||||||||||||
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* CSB7#/CKE5# ----------------------------------------+||||||||||||||||
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* CS[B7,A7,B6,A6]#/CKE[5342] -------------------------++++|||||||||||||
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* MECC[7:0] #2/#1 (100MHz) -------------------------++|||||||||||||||||
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* MD[63:0] #2/#1 (100MHz) ------------------------++|||||||||||||||||||
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* MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB# -+|||||||||||||||||||||
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@ -493,94 +586,55 @@ static void set_dram_buffer_strength(void)
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* ||||||||||||||||||||||||
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* 3 32 21 10 0 * 2 21 10 0
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* 9876543210987654321098765432109876543210 * 321098765432109876543210
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* a 10------------------------1010---------- * -1---------------11----- a
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*!a 11------------------------1111---------- * -0---------------00----- !a
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* b --10--------------------------1010------ * --1----------------11--- b
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*!b --11--------------------------1111------ * --0----------------00--- !b
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* c ----------------------------------1100-- * ----------------------1- c
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*!c ----------------------------------1011-- * ----------------------0- !c
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* 1 ----1010101000000000000000------------00 * ---11111111111111----1-0 1
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* 6 ----000000000000000000000010101010----00 * ---1111111111111100000-0 6
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* 10------------------------1111---------- a -1----------------------
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* 11------------------------1010---------- !a -0----------------------
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* --110000000010101010111111----1010--1010 * --01111000000000000000-0
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* ----------------------------------11---- c ----------------------1-
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* ----------------------------------10---- !c ----------------------0-
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* | | | | | | | | | | ||||||| | | | | | |
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* | | | | | | | | | | ||||||| | | | | | +- CKE0/FENA
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* | | | | | | | | | | ||||||| | | | | +--- CKE1/GCKE
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* | | | | | | | | | | ||||||| | | | | | +- CKE0
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* | | | | | | | | | | ||||||| | | | | +--- CKE1
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* | | | | | | | | | | ||||||| | | | +----- DQMA/CASA[764320]#
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* | | | | | | | | | | ||||||| | | +------- DQMB1/CASB1#
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* | | | | | | | | | | ||||||| | +--------- DQMB5/CASB5#
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* | | | | | | | | | | ||||||| +----------- DQMA1/CASA1#
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* | | | | | | | | | | ||||||+------------- DQMA5/CASA5#
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* | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# [ 0=1x;1=2x ]
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* | | | | | | | | | +--------------------- CSA6#/CKE2#
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* | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4#
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* | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3#
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* | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5#
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* | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (2x)
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* | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (2x)
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* | | | +--------------------------------- MD[63:0] #1 (2x)
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* | | +----------------------------------- MD[63:0] #2 (2x)
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* | +------------------------------------- MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
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* +--------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
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* MBSC[47:40] and MBFS[23] are reserved.
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*
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* This algorithm is checked against the ASUS P2B-LS (which has
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* 4 DIMM slots) factory BIOS.
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* Therefore it assumes a board with 4 slots, and will need testing
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* on boards with 3 DIMM slots.
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* | | | | | | | | | | ++++++-------------- CSA0-5#,CSB0-5# (2x)
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* | | | | | | | | | +--------------------- CSA6#/CKE2
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* | | | | | | | | +---[ MBSC ]------ CSB6#/CKE4
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* | | | | | | | +-----[ 00 = 1x ]------ CSA7#/CKE3
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* | | | | | | +-------[ 01 invalid ]------ CSB7#/CKE5
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* | | | | | +---------[ 10 = 2x ]------ MECC[7:0] #1 (1x)
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* | | | | +-----------[ 11 = 3x ]------ MECC[7:0] #2 (1x)
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* | | | +--------------------------------- MD[63:0] #1 (1x)
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* | | +----------------------------------- MD[63:0] #2 (1x)
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* | +------------------ MAB[12:11,9:0]#,MAB[13,10],WEB#,SRASB#,SCASB#
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* +------------------------------------- MAA[13:0],WEA#,SRASA#,SCASA#
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*/
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mbsc0 = 0x80;
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mbsc1 = 0x2a;
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mbfs2 = 0x1f;
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if (pci_read_config8(NB, NBXCFG + 1) & 0x30) {
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fsb = 66;
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mbsc3 = 0x00;
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mbsc4 = 0x00;
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mbfs0 = 0x80;
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} else {
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fsb = 100;
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mbsc3 = 0xa0;
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mbsc4 = 0x0a;
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mbfs0 = 0x84;
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}
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mbsc0 = 0xaa;
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mbsc1 = 0xafea;
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mbsc3 = 0xb00a;
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mbfs0 = 0x00;
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mbfs1 = 0x00;
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mbfs2 = 0x1e;
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if (dimm03 > 2) {
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mbsc4 = mbsc4 | 0x80;
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mbsc1 = mbsc1 | 0x28;
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mbfs2 = mbfs2 | 0x40;
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mbfs0 = mbfs0 | 0x60;
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mbsc1 |= 0x003c;
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mbfs2 |= 0x40;
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} else {
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mbsc4 = mbsc4 | 0xc0;
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if (fsb == 100) {
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mbsc1 = mbsc1 | 0x3c;
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}
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}
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if (dimm47 > 2) {
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mbsc4 = mbsc4 | 0x20;
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mbsc1 = mbsc1 | 0x02;
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mbsc0 = mbsc0 | 0x80;
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mbfs2 = mbfs2 | 0x20;
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mbfs0 = mbfs0 | 0x18;
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} else {
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mbsc4 = mbsc4 | 0x30;
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if (fsb == 100) {
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mbsc1 = mbsc1 | 0x03;
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mbsc0 = mbsc0 | 0xc0;
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}
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mbsc3 |= 0xc000;
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}
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if ((dimm03 + dimm47) > 4) {
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mbsc0 = mbsc0 | 0x30;
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mbfs0 = mbfs0 | 0x02;
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} else {
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mbsc0 = mbsc0 | 0x2c;
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mbsc0 |= 0x30;
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mbfs0 |= 0x02;
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}
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}
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pci_write_config8(NB, MBSC + 0, mbsc0);
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pci_write_config8(NB, MBSC + 1, mbsc1);
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pci_write_config8(NB, MBSC + 2, 0x00);
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pci_write_config8(NB, MBSC + 3, mbsc3);
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pci_write_config8(NB, MBSC + 4, mbsc4);
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pci_write_config8(NB, MBFS + 0, mbfs0);
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pci_write_config8(NB, MBFS + 1, 0xff);
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pci_write_config16(NB, MBSC + 1, mbsc1);
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pci_write_config16(NB, MBSC + 3, mbsc3);
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pci_write_config16(NB, MBFS + 0, mbfs1 << 8 | mbfs0);
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pci_write_config8(NB, MBFS + 2, mbfs2);
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}
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@ -683,7 +737,8 @@ static struct dimm_size spd_get_dimm_size(unsigned int device)
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sz.side1 *= 4;
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sz.side2 *= 4;
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/* It is possible to partially use larger then supported
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/*
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* It is possible to partially use larger than supported
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* modules by setting them to a supported size.
|
||||
*/
|
||||
if (sz.side1 > 128) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue