vc/amd/agesa: Delete mfParallelTraining.c
Potential for out-of-bounds read. However, this code is not used on F14, F15tn, or F16kb platforms. As can be seen in vc/amd/agesa/f15tn/Config/PlatformInstall.h only multiple socket F10 is supported. Tested on Lenovo G505s. Change-Id: Ib71fe32d89840b9f25619d74980e562fd626952b Signed-off-by: Joe Moore <awokd@danwin1210.me> Found-by: Coverity CID 1241831 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Joe Moore
Patrick Georgi
parent
c156b584ee
commit
a839581855
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@ -1,2 +1 @@
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libagesa-y += mfParallelTraining.c
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libagesa-y += mfStandardTraining.c
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libagesa-y += mfStandardTraining.c
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@ -1,286 +0,0 @@
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/* $NoKeywords:$ */
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/**
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* @file
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*
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* mfParallelTraining.c
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*
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* This is the parallel training feature
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*
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* @xrefitem bom "File Content Label" "Release Content"
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* @e project: AGESA
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* @e sub-project: (Mem/Feat/PARTRN)
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* @e \$Revision: 35136 $ @e \$Date: 2010-07-16 11:29:48 +0800 (Fri, 16 Jul 2010) $
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*
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**/
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/*
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*****************************************************************************
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*
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* Copyright (c) 2011, Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Advanced Micro Devices, Inc. nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* ***************************************************************************
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*
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "OptionMemory.h"
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#include "mm.h"
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#include "mn.h"
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#include "Ids.h"
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#include "cpuRegisters.h"
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#include "cpuApicUtilities.h"
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#include "mfParallelTraining.h"
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#include "heapManager.h"
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#include "GeneralServices.h"
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#include "Filecode.h"
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CODE_GROUP (G2_PEI)
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RDATA_GROUP (G2_PEI)
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#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
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/*-----------------------------------------------------------------------------
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* EXPORTED FUNCTIONS
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*
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*-----------------------------------------------------------------------------
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*/
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extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
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/* -----------------------------------------------------------------------------*/
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/**
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*
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*
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* This is the main function to perform parallel training on all nodes.
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* This is the routine which will run on the remote AP.
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*
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* @param[in,out] *EnvPtr - Pointer to the Training Environment Data
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* @param[in,out] *StdHeader - Pointer to the Standard Header of the AP
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*
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* @return TRUE - This feature is enabled.
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* @return FALSE - This feature is not enabled.
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*/
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BOOLEAN
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MemFParallelTraining (
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IN OUT REMOTE_TRAINING_ENV *EnvPtr,
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IN OUT AMD_CONFIG_PARAMS *StdHeader
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)
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{
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MEM_PARAMETER_STRUCT ParameterList;
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MEM_NB_BLOCK NB;
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MEM_TECH_BLOCK TB;
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ALLOCATE_HEAP_PARAMS AllocHeapParams;
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MEM_DATA_STRUCT *MemPtr;
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DIE_STRUCT *MCTPtr;
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UINT8 p;
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UINT8 i;
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UINT8 Dct;
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UINT8 Channel;
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UINT8 *BufferPtr;
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UINT8 DctCount;
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UINT8 ChannelCount;
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UINT8 RowCount;
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UINT8 ColumnCount;
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UINT16 SizeOfNewBuffer;
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AP_DATA_TRANSFER ReturnData;
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//
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// Initialize Parameters
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//
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ReturnData.DataPtr = NULL;
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ReturnData.DataSizeInDwords = 0;
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ReturnData.DataTransferFlags = 0;
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ASSERT (EnvPtr != NULL);
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//
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// Replace Standard header of a AP
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//
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LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
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//
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// Allocate buffer for training data
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//
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BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
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DctCount = EnvPtr->DieStruct.DctCount;
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BufferPtr += sizeof (DIE_STRUCT);
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ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
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BufferPtr += DctCount * sizeof (DCT_STRUCT);
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RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
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ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
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SizeOfNewBuffer = sizeof (DIE_STRUCT) +
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DctCount * (
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sizeof (DCT_STRUCT) + (
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ChannelCount * (
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sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
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RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
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(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
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)
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)
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)
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);
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AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
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AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
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AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
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if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
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BufferPtr = AllocHeapParams.BufferPtr;
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LibAmdMemCopy ( BufferPtr,
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&(EnvPtr->DieStruct),
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sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
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StdHeader
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);
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//
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// Fix up pointers
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//
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MCTPtr = (DIE_STRUCT *) BufferPtr;
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BufferPtr += sizeof (DIE_STRUCT);
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MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
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BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
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for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
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MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
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BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
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for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
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MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
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MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
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}
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}
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NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
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BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
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ReturnData.DataPtr = AllocHeapParams.BufferPtr;
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ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
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ReturnData.DataTransferFlags = 0;
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//
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// Allocate Memory for the MEM_DATA_STRUCT we will use
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//
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AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
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AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
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AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
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if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
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MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
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LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
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//
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// Copy Parameters from environment
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//
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ParameterList.HoleBase = EnvPtr->HoleBase;
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ParameterList.BottomIo = EnvPtr->BottomIo;
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ParameterList.UmaSize = EnvPtr->UmaSize;
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ParameterList.SysLimit = EnvPtr->SysLimit;
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ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
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ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
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MemPtr->ParameterListPtr = &ParameterList;
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for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
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MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
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}
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MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
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//
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// Create Local NBBlock and Tech Block
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//
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EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
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NB.RefPtr = &ParameterList;
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NB.MemPtr = MemPtr;
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i = 0;
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while (memTechInstalled[i] != NULL) {
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if (memTechInstalled[i] (&TB, &NB)) {
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break;
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}
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i++;
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}
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NB.TechPtr = &TB;
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NB.TechBlockSwitch (&NB);
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//
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// Setup CPU Mem Type MSRs on the AP
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//
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NB.CpuMemTyping (&NB);
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IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
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//
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// Call Technology Specific Training routine
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//
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NB.TrainingFlow (&NB);
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//
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// Copy training data to ReturnData buffer
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//
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LibAmdMemCopy ( BufferPtr,
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MCTPtr->DctData[0].ChData[0].RcvEnDlys,
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((DctCount * ChannelCount) * (
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(RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
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(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES)
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)
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),
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StdHeader);
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HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
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//
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// Restore pointers
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//
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for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
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for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
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MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
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MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
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MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
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MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
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MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
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MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
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MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
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MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
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MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
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MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
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MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
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}
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MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
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}
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MCTPtr->DctData = EnvPtr->DieStruct.DctData;
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}
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//
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// Signal to BSP that training is complete and Send Results
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//
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ASSERT (ReturnData.DataPtr != NULL);
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ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
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//
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// Clean up and exit.
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//
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HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
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} else {
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MCTPtr = &EnvPtr->DieStruct;
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PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
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SetMemError (AGESA_FATAL, MCTPtr);
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ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
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}
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return TRUE;
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}
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@ -104,12 +104,6 @@ typedef struct _DIE_INFO {
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*----------------------------------------------------------------------------
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*----------------------------------------------------------------------------
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*/
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*/
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BOOLEAN
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MemFParallelTraining (
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IN OUT REMOTE_TRAINING_ENV *EnvPtr,
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IN OUT AMD_CONFIG_PARAMS *StdHeader
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);
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#endif /* _MFPARALLELTRAINING_H_ */
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#endif /* _MFPARALLELTRAINING_H_ */
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@ -1,2 +1 @@
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libagesa-y += mfParallelTraining.c
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libagesa-y += mfStandardTraining.c
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libagesa-y += mfStandardTraining.c
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@ -1,288 +0,0 @@
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/* $NoKeywords:$ */
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/**
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|
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* @file
|
|
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*
|
|
||||||
* mfParallelTraining.c
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*
|
|
||||||
* This is the parallel training feature
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||||||
*
|
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||||||
* @xrefitem bom "File Content Label" "Release Content"
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|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: (Mem/Feat/PARTRN)
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||||||
* @e \$Revision: 63425 $ @e \$Date: 2011-12-22 11:24:10 -0600 (Thu, 22 Dec 2011) $
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*
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**/
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/*****************************************************************************
|
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*
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* Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
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* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* ***************************************************************************
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "AGESA.h"
|
|
||||||
#include "amdlib.h"
|
|
||||||
#include "OptionMemory.h"
|
|
||||||
#include "mm.h"
|
|
||||||
#include "mn.h"
|
|
||||||
#include "Ids.h"
|
|
||||||
#include "cpuRegisters.h"
|
|
||||||
#include "cpuApicUtilities.h"
|
|
||||||
#include "mfParallelTraining.h"
|
|
||||||
#include "heapManager.h"
|
|
||||||
#include "GeneralServices.h"
|
|
||||||
#include "Filecode.h"
|
|
||||||
CODE_GROUP (G2_PEI)
|
|
||||||
RDATA_GROUP (G2_PEI)
|
|
||||||
|
|
||||||
#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------
|
|
||||||
* EXPORTED FUNCTIONS
|
|
||||||
*
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
|
|
||||||
|
|
||||||
/* -----------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* This is the main function to perform parallel training on all nodes.
|
|
||||||
* This is the routine which will run on the remote AP.
|
|
||||||
*
|
|
||||||
* @param[in,out] *EnvPtr - Pointer to the Training Environment Data
|
|
||||||
* @param[in,out] *StdHeader - Pointer to the Standard Header of the AP
|
|
||||||
*
|
|
||||||
* @return TRUE - This feature is enabled.
|
|
||||||
* @return FALSE - This feature is not enabled.
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
MemFParallelTraining (
|
|
||||||
IN OUT REMOTE_TRAINING_ENV *EnvPtr,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
MEM_PARAMETER_STRUCT ParameterList;
|
|
||||||
MEM_NB_BLOCK NB;
|
|
||||||
MEM_TECH_BLOCK TB;
|
|
||||||
ALLOCATE_HEAP_PARAMS AllocHeapParams;
|
|
||||||
MEM_DATA_STRUCT *MemPtr;
|
|
||||||
DIE_STRUCT *MCTPtr;
|
|
||||||
UINT8 p;
|
|
||||||
UINT8 i;
|
|
||||||
UINT8 Dct;
|
|
||||||
UINT8 Channel;
|
|
||||||
UINT8 *BufferPtr;
|
|
||||||
UINT8 DctCount;
|
|
||||||
UINT8 ChannelCount;
|
|
||||||
UINT8 RowCount;
|
|
||||||
UINT8 ColumnCount;
|
|
||||||
UINT16 SizeOfNewBuffer;
|
|
||||||
AP_DATA_TRANSFER ReturnData;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Initialize Parameters
|
|
||||||
//
|
|
||||||
ReturnData.DataPtr = NULL;
|
|
||||||
ReturnData.DataSizeInDwords = 0;
|
|
||||||
ReturnData.DataTransferFlags = 0;
|
|
||||||
|
|
||||||
ASSERT (EnvPtr != NULL);
|
|
||||||
//
|
|
||||||
// Replace Standard header of a AP
|
|
||||||
//
|
|
||||||
LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
|
|
||||||
|
|
||||||
|
|
||||||
//
|
|
||||||
// Allocate buffer for training data
|
|
||||||
//
|
|
||||||
BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
|
|
||||||
DctCount = EnvPtr->DieStruct.DctCount;
|
|
||||||
BufferPtr += sizeof (DIE_STRUCT);
|
|
||||||
ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
|
|
||||||
BufferPtr += DctCount * sizeof (DCT_STRUCT);
|
|
||||||
RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
|
|
||||||
ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
|
|
||||||
|
|
||||||
SizeOfNewBuffer = sizeof (DIE_STRUCT) +
|
|
||||||
DctCount * (
|
|
||||||
sizeof (DCT_STRUCT) + (
|
|
||||||
ChannelCount * (
|
|
||||||
sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
|
|
||||||
RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
|
|
||||||
(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
|
|
||||||
(MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
|
|
||||||
)
|
|
||||||
)
|
|
||||||
)
|
|
||||||
);
|
|
||||||
AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
|
|
||||||
AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
|
|
||||||
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
|
|
||||||
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
|
|
||||||
BufferPtr = AllocHeapParams.BufferPtr;
|
|
||||||
LibAmdMemCopy ( BufferPtr,
|
|
||||||
&(EnvPtr->DieStruct),
|
|
||||||
sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
|
|
||||||
StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Fix up pointers
|
|
||||||
//
|
|
||||||
MCTPtr = (DIE_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += sizeof (DIE_STRUCT);
|
|
||||||
MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
|
|
||||||
for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
|
|
||||||
for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
|
|
||||||
BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
|
|
||||||
|
|
||||||
ReturnData.DataPtr = AllocHeapParams.BufferPtr;
|
|
||||||
ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
|
|
||||||
ReturnData.DataTransferFlags = 0;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Allocate Memory for the MEM_DATA_STRUCT we will use
|
|
||||||
//
|
|
||||||
AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
|
|
||||||
AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
|
|
||||||
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
|
|
||||||
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
|
|
||||||
MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
|
|
||||||
|
|
||||||
LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Copy Parameters from environment
|
|
||||||
//
|
|
||||||
ParameterList.HoleBase = EnvPtr->HoleBase;
|
|
||||||
ParameterList.BottomIo = EnvPtr->BottomIo;
|
|
||||||
ParameterList.UmaSize = EnvPtr->UmaSize;
|
|
||||||
ParameterList.SysLimit = EnvPtr->SysLimit;
|
|
||||||
ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
|
|
||||||
ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
|
|
||||||
MemPtr->ParameterListPtr = &ParameterList;
|
|
||||||
|
|
||||||
for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
|
|
||||||
MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
|
|
||||||
}
|
|
||||||
|
|
||||||
MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
|
|
||||||
//
|
|
||||||
// Create Local NBBlock and Tech Block
|
|
||||||
//
|
|
||||||
EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
|
|
||||||
NB.RefPtr = &ParameterList;
|
|
||||||
NB.MemPtr = MemPtr;
|
|
||||||
i = 0;
|
|
||||||
while (memTechInstalled[i] != NULL) {
|
|
||||||
if (memTechInstalled[i] (&TB, &NB)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
i++;
|
|
||||||
}
|
|
||||||
NB.TechPtr = &TB;
|
|
||||||
NB.TechBlockSwitch (&NB);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Setup CPU Mem Type MSRs on the AP
|
|
||||||
//
|
|
||||||
NB.CpuMemTyping (&NB);
|
|
||||||
|
|
||||||
IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
|
|
||||||
//
|
|
||||||
// Call Technology Specific Training routine
|
|
||||||
//
|
|
||||||
NB.TrainingFlow (&NB);
|
|
||||||
//
|
|
||||||
// Copy training data to ReturnData buffer
|
|
||||||
//
|
|
||||||
LibAmdMemCopy ( BufferPtr,
|
|
||||||
MCTPtr->DctData[0].ChData[0].RcvEnDlys,
|
|
||||||
((DctCount * ChannelCount) * (
|
|
||||||
(RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
|
|
||||||
(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
|
|
||||||
(MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
|
|
||||||
)
|
|
||||||
),
|
|
||||||
StdHeader);
|
|
||||||
|
|
||||||
HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
|
|
||||||
//
|
|
||||||
// Restore pointers
|
|
||||||
//
|
|
||||||
for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
|
|
||||||
for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
|
|
||||||
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
|
|
||||||
}
|
|
||||||
MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
|
|
||||||
}
|
|
||||||
MCTPtr->DctData = EnvPtr->DieStruct.DctData;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Signal to BSP that training is complete and Send Results
|
|
||||||
//
|
|
||||||
ASSERT (ReturnData.DataPtr != NULL);
|
|
||||||
ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Clean up and exit.
|
|
||||||
//
|
|
||||||
HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
|
|
||||||
} else {
|
|
||||||
MCTPtr = &EnvPtr->DieStruct;
|
|
||||||
PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
|
|
||||||
SetMemError (AGESA_FATAL, MCTPtr);
|
|
||||||
ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
|
|
||||||
}
|
|
||||||
return TRUE;
|
|
||||||
}
|
|
||||||
|
|
@ -102,12 +102,6 @@ typedef struct _DIE_INFO {
|
||||||
*----------------------------------------------------------------------------
|
*----------------------------------------------------------------------------
|
||||||
*/
|
*/
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
MemFParallelTraining (
|
|
||||||
IN OUT REMOTE_TRAINING_ENV *EnvPtr,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif /* _MFPARALLELTRAINING_H_ */
|
#endif /* _MFPARALLELTRAINING_H_ */
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -1,2 +1 @@
|
||||||
libagesa-y += mfParallelTraining.c
|
|
||||||
libagesa-y += mfStandardTraining.c
|
libagesa-y += mfStandardTraining.c
|
||||||
|
|
|
||||||
|
|
@ -1,288 +0,0 @@
|
||||||
/* $NoKeywords:$ */
|
|
||||||
/**
|
|
||||||
* @file
|
|
||||||
*
|
|
||||||
* mfParallelTraining.c
|
|
||||||
*
|
|
||||||
* This is the parallel training feature
|
|
||||||
*
|
|
||||||
* @xrefitem bom "File Content Label" "Release Content"
|
|
||||||
* @e project: AGESA
|
|
||||||
* @e sub-project: (Mem/Feat/PARTRN)
|
|
||||||
* @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
|
|
||||||
*
|
|
||||||
**/
|
|
||||||
/*****************************************************************************
|
|
||||||
*
|
|
||||||
* Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
|
|
||||||
* All rights reserved.
|
|
||||||
*
|
|
||||||
* Redistribution and use in source and binary forms, with or without
|
|
||||||
* modification, are permitted provided that the following conditions are met:
|
|
||||||
* * Redistributions of source code must retain the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer.
|
|
||||||
* * Redistributions in binary form must reproduce the above copyright
|
|
||||||
* notice, this list of conditions and the following disclaimer in the
|
|
||||||
* documentation and/or other materials provided with the distribution.
|
|
||||||
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
|
|
||||||
* its contributors may be used to endorse or promote products derived
|
|
||||||
* from this software without specific prior written permission.
|
|
||||||
*
|
|
||||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
|
||||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
|
||||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
|
||||||
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
|
|
||||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
||||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
||||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
||||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
||||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
||||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
||||||
* ***************************************************************************
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
#include "AGESA.h"
|
|
||||||
#include "amdlib.h"
|
|
||||||
#include "OptionMemory.h"
|
|
||||||
#include "mm.h"
|
|
||||||
#include "mn.h"
|
|
||||||
#include "Ids.h"
|
|
||||||
#include "cpuRegisters.h"
|
|
||||||
#include "cpuApicUtilities.h"
|
|
||||||
#include "mfParallelTraining.h"
|
|
||||||
#include "heapManager.h"
|
|
||||||
#include "GeneralServices.h"
|
|
||||||
#include "Filecode.h"
|
|
||||||
CODE_GROUP (G2_PEI)
|
|
||||||
RDATA_GROUP (G2_PEI)
|
|
||||||
|
|
||||||
#define FILECODE PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------------
|
|
||||||
* EXPORTED FUNCTIONS
|
|
||||||
*
|
|
||||||
*-----------------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
extern MEM_TECH_CONSTRUCTOR* memTechInstalled[];
|
|
||||||
|
|
||||||
/* -----------------------------------------------------------------------------*/
|
|
||||||
/**
|
|
||||||
*
|
|
||||||
*
|
|
||||||
* This is the main function to perform parallel training on all nodes.
|
|
||||||
* This is the routine which will run on the remote AP.
|
|
||||||
*
|
|
||||||
* @param[in,out] *EnvPtr - Pointer to the Training Environment Data
|
|
||||||
* @param[in,out] *StdHeader - Pointer to the Standard Header of the AP
|
|
||||||
*
|
|
||||||
* @return TRUE - This feature is enabled.
|
|
||||||
* @return FALSE - This feature is not enabled.
|
|
||||||
*/
|
|
||||||
BOOLEAN
|
|
||||||
MemFParallelTraining (
|
|
||||||
IN OUT REMOTE_TRAINING_ENV *EnvPtr,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
)
|
|
||||||
{
|
|
||||||
MEM_PARAMETER_STRUCT ParameterList;
|
|
||||||
MEM_NB_BLOCK NB;
|
|
||||||
MEM_TECH_BLOCK TB;
|
|
||||||
ALLOCATE_HEAP_PARAMS AllocHeapParams;
|
|
||||||
MEM_DATA_STRUCT *MemPtr;
|
|
||||||
DIE_STRUCT *MCTPtr;
|
|
||||||
UINT8 p;
|
|
||||||
UINT8 i;
|
|
||||||
UINT8 Dct;
|
|
||||||
UINT8 Channel;
|
|
||||||
UINT8 *BufferPtr;
|
|
||||||
UINT8 DctCount;
|
|
||||||
UINT8 ChannelCount;
|
|
||||||
UINT8 RowCount;
|
|
||||||
UINT8 ColumnCount;
|
|
||||||
UINT16 SizeOfNewBuffer;
|
|
||||||
AP_DATA_TRANSFER ReturnData;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Initialize Parameters
|
|
||||||
//
|
|
||||||
ReturnData.DataPtr = NULL;
|
|
||||||
ReturnData.DataSizeInDwords = 0;
|
|
||||||
ReturnData.DataTransferFlags = 0;
|
|
||||||
|
|
||||||
ASSERT (EnvPtr != NULL);
|
|
||||||
//
|
|
||||||
// Replace Standard header of a AP
|
|
||||||
//
|
|
||||||
LibAmdMemCopy (StdHeader, &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), &(EnvPtr->StdHeader));
|
|
||||||
|
|
||||||
|
|
||||||
//
|
|
||||||
// Allocate buffer for training data
|
|
||||||
//
|
|
||||||
BufferPtr = (UINT8 *) (&EnvPtr->DieStruct);
|
|
||||||
DctCount = EnvPtr->DieStruct.DctCount;
|
|
||||||
BufferPtr += sizeof (DIE_STRUCT);
|
|
||||||
ChannelCount = ((DCT_STRUCT *) BufferPtr)->ChannelCount;
|
|
||||||
BufferPtr += DctCount * sizeof (DCT_STRUCT);
|
|
||||||
RowCount = ((CH_DEF_STRUCT *) BufferPtr)->RowCount;
|
|
||||||
ColumnCount = ((CH_DEF_STRUCT *) BufferPtr)->ColumnCount;
|
|
||||||
|
|
||||||
SizeOfNewBuffer = sizeof (DIE_STRUCT) +
|
|
||||||
DctCount * (
|
|
||||||
sizeof (DCT_STRUCT) + (
|
|
||||||
ChannelCount * (
|
|
||||||
sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK) + (
|
|
||||||
RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES +
|
|
||||||
(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
|
|
||||||
(MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
|
|
||||||
)
|
|
||||||
)
|
|
||||||
)
|
|
||||||
);
|
|
||||||
AllocHeapParams.RequestedBufferSize = SizeOfNewBuffer;
|
|
||||||
AllocHeapParams.BufferHandle = GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0);
|
|
||||||
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
|
|
||||||
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
|
|
||||||
BufferPtr = AllocHeapParams.BufferPtr;
|
|
||||||
LibAmdMemCopy ( BufferPtr,
|
|
||||||
&(EnvPtr->DieStruct),
|
|
||||||
sizeof (DIE_STRUCT) + DctCount * (sizeof (DCT_STRUCT) + ChannelCount * (sizeof (CH_DEF_STRUCT) + sizeof (MEM_PS_BLOCK))),
|
|
||||||
StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Fix up pointers
|
|
||||||
//
|
|
||||||
MCTPtr = (DIE_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += sizeof (DIE_STRUCT);
|
|
||||||
MCTPtr->DctData = (DCT_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += MCTPtr->DctCount * sizeof (DCT_STRUCT);
|
|
||||||
for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData = (CH_DEF_STRUCT *) BufferPtr;
|
|
||||||
BufferPtr += MCTPtr->DctData[Dct].ChannelCount * sizeof (CH_DEF_STRUCT);
|
|
||||||
for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = MCTPtr;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &MCTPtr->DctData[Dct];
|
|
||||||
}
|
|
||||||
}
|
|
||||||
NB.PSBlock = (MEM_PS_BLOCK *) BufferPtr;
|
|
||||||
BufferPtr += DctCount * ChannelCount * sizeof (MEM_PS_BLOCK);
|
|
||||||
|
|
||||||
ReturnData.DataPtr = AllocHeapParams.BufferPtr;
|
|
||||||
ReturnData.DataSizeInDwords = (SizeOfNewBuffer + 3) / 4;
|
|
||||||
ReturnData.DataTransferFlags = 0;
|
|
||||||
|
|
||||||
//
|
|
||||||
// Allocate Memory for the MEM_DATA_STRUCT we will use
|
|
||||||
//
|
|
||||||
AllocHeapParams.RequestedBufferSize = sizeof (MEM_DATA_STRUCT);
|
|
||||||
AllocHeapParams.BufferHandle = AMD_MEM_DATA_HANDLE;
|
|
||||||
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
|
|
||||||
if (HeapAllocateBuffer (&AllocHeapParams, StdHeader) == AGESA_SUCCESS) {
|
|
||||||
MemPtr = (MEM_DATA_STRUCT *)AllocHeapParams.BufferPtr;
|
|
||||||
|
|
||||||
LibAmdMemCopy (&(MemPtr->StdHeader), &(EnvPtr->StdHeader), sizeof (AMD_CONFIG_PARAMS), StdHeader);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Copy Parameters from environment
|
|
||||||
//
|
|
||||||
ParameterList.HoleBase = EnvPtr->HoleBase;
|
|
||||||
ParameterList.BottomIo = EnvPtr->BottomIo;
|
|
||||||
ParameterList.UmaSize = EnvPtr->UmaSize;
|
|
||||||
ParameterList.SysLimit = EnvPtr->SysLimit;
|
|
||||||
ParameterList.TableBasedAlterations = EnvPtr->TableBasedAlterations;
|
|
||||||
ParameterList.PlatformMemoryConfiguration = EnvPtr->PlatformMemoryConfiguration;
|
|
||||||
MemPtr->ParameterListPtr = &ParameterList;
|
|
||||||
|
|
||||||
for (p = 0; p < MAX_PLATFORM_TYPES; p++) {
|
|
||||||
MemPtr->GetPlatformCfg[p] = EnvPtr->GetPlatformCfg[p];
|
|
||||||
}
|
|
||||||
|
|
||||||
MemPtr->ErrorHandling = EnvPtr->ErrorHandling;
|
|
||||||
//
|
|
||||||
// Create Local NBBlock and Tech Block
|
|
||||||
//
|
|
||||||
EnvPtr->NBBlockCtor (&NB, MCTPtr, EnvPtr->FeatPtr);
|
|
||||||
NB.RefPtr = &ParameterList;
|
|
||||||
NB.MemPtr = MemPtr;
|
|
||||||
i = 0;
|
|
||||||
while (memTechInstalled[i] != NULL) {
|
|
||||||
if (memTechInstalled[i] (&TB, &NB)) {
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
i++;
|
|
||||||
}
|
|
||||||
NB.TechPtr = &TB;
|
|
||||||
NB.TechBlockSwitch (&NB);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Setup CPU Mem Type MSRs on the AP
|
|
||||||
//
|
|
||||||
NB.CpuMemTyping (&NB);
|
|
||||||
|
|
||||||
IDS_HDT_CONSOLE (MEM_STATUS, "Node %d\n", NB.Node);
|
|
||||||
//
|
|
||||||
// Call Technology Specific Training routine
|
|
||||||
//
|
|
||||||
NB.TrainingFlow (&NB);
|
|
||||||
//
|
|
||||||
// Copy training data to ReturnData buffer
|
|
||||||
//
|
|
||||||
LibAmdMemCopy ( BufferPtr,
|
|
||||||
MCTPtr->DctData[0].ChData[0].RcvEnDlys,
|
|
||||||
((DctCount * ChannelCount) * (
|
|
||||||
(RowCount * ColumnCount * NUMBER_OF_DELAY_TABLES) +
|
|
||||||
(MAX_BYTELANES_PER_CHANNEL * MAX_CS_PER_CHANNEL * NUMBER_OF_FAILURE_MASK_TABLES) +
|
|
||||||
(MAX_DIMMS_PER_CHANNEL * MAX_NUMBER_LANES)
|
|
||||||
)
|
|
||||||
),
|
|
||||||
StdHeader);
|
|
||||||
|
|
||||||
HeapDeallocateBuffer (AMD_MEM_DATA_HANDLE, StdHeader);
|
|
||||||
//
|
|
||||||
// Restore pointers
|
|
||||||
//
|
|
||||||
for (Dct = 0; Dct < MCTPtr->DctCount; Dct++) {
|
|
||||||
for (Channel = 0; Channel < MCTPtr->DctData[Dct].ChannelCount; Channel++) {
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].MCTPtr = &EnvPtr->DieStruct;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].DCTPtr = &EnvPtr->DieStruct.DctData[Dct];
|
|
||||||
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RcvEnDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RcvEnDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqs2dDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqs2dDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMinDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].RdDqsMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].RdDqsMaxDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatMinDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMinDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].WrDatMaxDlys = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].WrDatMaxDlys;
|
|
||||||
MCTPtr->DctData[Dct].ChData[Channel].FailingBitMask = EnvPtr->DieStruct.DctData[Dct].ChData[Channel].FailingBitMask;
|
|
||||||
}
|
|
||||||
MCTPtr->DctData[Dct].ChData = EnvPtr->DieStruct.DctData[Dct].ChData;
|
|
||||||
}
|
|
||||||
MCTPtr->DctData = EnvPtr->DieStruct.DctData;
|
|
||||||
}
|
|
||||||
|
|
||||||
//
|
|
||||||
// Signal to BSP that training is complete and Send Results
|
|
||||||
//
|
|
||||||
ASSERT (ReturnData.DataPtr != NULL);
|
|
||||||
ApUtilTransmitBuffer (EnvPtr->BspSocket, EnvPtr->BspCore, &ReturnData, StdHeader);
|
|
||||||
|
|
||||||
//
|
|
||||||
// Clean up and exit.
|
|
||||||
//
|
|
||||||
HeapDeallocateBuffer (GENERATE_MEM_HANDLE (ALLOC_PAR_TRN_HANDLE, 0, 0, 0), StdHeader);
|
|
||||||
} else {
|
|
||||||
MCTPtr = &EnvPtr->DieStruct;
|
|
||||||
PutEventLog (AGESA_FATAL, MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA, MCTPtr->NodeId, 0, 0, 0, StdHeader);
|
|
||||||
SetMemError (AGESA_FATAL, MCTPtr);
|
|
||||||
ASSERT(FALSE); // Could not allocate heap for buffer for parallel training data
|
|
||||||
}
|
|
||||||
return TRUE;
|
|
||||||
}
|
|
||||||
|
|
@ -102,12 +102,6 @@ typedef struct _DIE_INFO {
|
||||||
*----------------------------------------------------------------------------
|
*----------------------------------------------------------------------------
|
||||||
*/
|
*/
|
||||||
|
|
||||||
BOOLEAN
|
|
||||||
MemFParallelTraining (
|
|
||||||
IN OUT REMOTE_TRAINING_ENV *EnvPtr,
|
|
||||||
IN OUT AMD_CONFIG_PARAMS *StdHeader
|
|
||||||
);
|
|
||||||
|
|
||||||
#endif /* _MFPARALLELTRAINING_H_ */
|
#endif /* _MFPARALLELTRAINING_H_ */
|
||||||
|
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue