for different pll values.

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/amd/rumba/auto.c

@@ -42,7 +42,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
 
 #define PLLMSRhi 0x00001490
 #define PLLMSRlo 0x02000030
-#define PLLMSRhi2 ((0xde << 16) | (1 << 26) | (1 << 24))
+#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
 #define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
 #include "northbridge/amd/gx2/pll_reset.c"
 

src/mainboard/lippert/frontrunner/auto.c

@@ -42,6 +42,10 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
 #include "northbridge/amd/gx2/raminit.c"
 #include "sdram/generic_sdram.c"
 
+#define PLLMSRhi 0x00000226
+#define PLLMSRlo 0x81000048
+#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
+#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
 #include "northbridge/amd/gx2/pll_reset.c"
 
 

src/northbridge/amd/gx2/pll_reset.c

@@ -136,7 +136,7 @@ static void pll_reset(void)
 		msr.hi = PLLMSRhi;
 		msr.lo = PLLMSRlo;
 		wrmsr(GLCP_SYS_RSTPLL, msr);
-		msr.lo |= PLLMSRhi2;
+		msr.lo |= PLLMSRlo1;
 		wrmsr(GLCP_SYS_RSTPLL, msr);
 
 		print_debug("Reset PLL\n\r");