mb/google/myst: Add new mainboard

Myst is a new Google mainboard with an AMD Phoenix SOC.

BUG=b:270596106
TEST=util/abuild/abuild -t GOOGLE_MYST --clean

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>

src/mainboard/google/myst/Kconfig

@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+config BOARD_GOOGLE_BASEBOARD_MYST
+	def_bool n
+
+if BOARD_GOOGLE_BASEBOARD_MYST
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select SOC_AMD_PHOENIX
+
+config DEVICETREE
+	default "variants/baseboard/devicetree.cb"
+
+config FMDFILE
+	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd"
+
+config MAINBOARD_DIR
+	default "google/myst"
+
+config MAINBOARD_FAMILY
+	string
+	default "Google_Myst"
+
+config MAINBOARD_PART_NUMBER
+	default "Myst" if BOARD_GOOGLE_MYST
+
+endif # BOARD_GOOGLE_BASEBOARD_MYST

src/mainboard/google/myst/Kconfig.name

@@ -0,0 +1,5 @@
+comment "Myst"
+
+config BOARD_GOOGLE_MYST
+	bool "->  Myst"
+	select BOARD_GOOGLE_BASEBOARD_MYST

src/mainboard/google/myst/Makefile.inc

@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += bootblock.c
+
+romstage-y += port_descriptors.c
+
+ramstage-y += mainboard.c
+ramstage-y += port_descriptors.c
+
+subdirs-y += variants/baseboard
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include

src/mainboard/google/myst/board_info.txt

@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Myst
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/google/myst/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <baseboard/variants.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	/* TODO(b/275959717): Perform mainboard initialization */
+}

src/mainboard/google/myst/chromeos.fmd

@@ -0,0 +1,39 @@
+# TODO(b/276944900): Update for 32 MB support, evaluate WP_RO size
+FLASH@0xFF000000 16M {
+	SI_BIOS {
+		WP_RO 8M {
+			RO_GSCVD 8K
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				COREBOOT(CBFS)
+				GBB 12K
+			}
+		}
+		RW_SECTION_A 3M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			SIGNED_AMDFW_A 1536K
+			RW_FWID_A 256
+		}
+		RW_SECTION_B 3M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			SIGNED_AMDFW_B 1536K
+			RW_FWID_B 256
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 16K {
+			SHARED_DATA 8K
+			VBLOCK_DEV 8K
+		}
+		RW_VPD(PRESERVE) 8K
+		RW_NVRAM(PRESERVE) 20K
+		SMMSTORE(PRESERVE) 64K
+		RW_LEGACY(CBFS)
+		RW_VBIOS_CACHE 64K
+		RW_MRC_CACHE(PRESERVE) 256K
+		RECOVERY_MRC_CACHE(PRESERVE) 256K
+	}
+}

src/mainboard/google/myst/dsdt.asl

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc.asl>
+}

src/mainboard/google/myst/mainboard.c

@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <amdblocks/amd_pci_util.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+
+static const struct fch_irq_routing fch_irq_map[] = {
+	{ 0,	0x00,		0x00 },
+};
+
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+{
+	*length = ARRAY_SIZE(fch_irq_map);
+	return fch_irq_map;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	/* TODO(b/270596581): Perform mainboard initialization */
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	/* TODO(b/270618107): Enable mainboard */
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/google/myst/port_descriptors.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/platform_descriptors.h>
+#include <types.h>
+
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+	/* TODO(b/276744321): Initialize DXIO and DDI descriptors */
+}

src/mainboard/google/myst/variants/baseboard/devicetree.cb

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+chip soc/amd/phoenix
+	device domain 0 on end # domain
+end	# chip soc/amd/phoenix

src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h

@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#endif /* __BASEBOARD_VARIANTS_H__ */