mb/google/rex/variants/deku: Complete USB configuration
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Eran Mitrani
Matt DeVillier
parent
3bad203be1
commit
a8636ae86b
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@ -98,6 +98,158 @@ chip soc/intel/meteorlake
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end # PCIE11 SSD card
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device ref tbt_pcie_rp0 on end
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device ref tbt_pcie_rp1 on end
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device ref tbt_pcie_rp2 on end
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device ref tbt_pcie_rp3 on end
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device ref tcss_xhci on
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chip drivers/usb/acpi
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device ref tcss_root_hub on
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
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device ref tcss_usb3_port0 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref tcss_usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
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device ref tcss_usb3_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-C Port C3""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref tcss_usb3_port2 on end
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end
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end
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end
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end
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device ref tcss_dma0 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port0 as dfp[0].typec_port
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device generic 0 on end
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end
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chip drivers/intel/usb4/retimer
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register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port1 as dfp[1].typec_port
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device generic 0 on end
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end
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end
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device ref tcss_dma1 on
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chip drivers/intel/usb4/retimer
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register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port2 as dfp[0].typec_port
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device generic 0 on end
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end
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chip drivers/intel/usb4/retimer
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register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
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use tcss_usb3_port3 as dfp[0].typec_port
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device generic 0 on end
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end
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end
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device ref xhci on
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chip drivers/usb/acpi
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device ref xhci_root_hub on
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# FIXME - location need to be corrected once we have the final design
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C0""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
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device ref usb2_port2 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C1""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
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device ref usb2_port3 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C2""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(3, 1))"
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device ref usb2_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-C Port C3""
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register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
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device ref usb2_port5 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A0""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))"
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device ref usb2_port4 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A1""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))"
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device ref usb2_port7 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A2""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(5, 3))"
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device ref usb2_port8 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A3""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))"
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device ref usb2_port9 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Type-A Port A4""
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register "type" = "UPC_TYPE_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 4))"
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device ref usb2_port6 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB2 Bluetooth""
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register "type" = "UPC_TYPE_INTERNAL"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B01)"
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device ref usb2_port10 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A0""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(5, 1))"
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device ref usb3_port1 on end
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end
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chip drivers/usb/acpi
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register "desc" = ""USB3 Type-A Port A1""
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register "type" = "UPC_TYPE_USB3_A"
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register "use_custom_pld" = "true"
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register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(5, 2))"
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device ref usb3_port2 on end
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end
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end
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end
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end
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device ref i2c4 on
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chip drivers/i2c/tpm
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register "hid" = ""GOOG0005""
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@ -105,6 +257,44 @@ chip soc/intel/meteorlake
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device i2c 50 on end
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end
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end
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device ref soc_espi on
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chip ec/google/chromeec
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use conn0 as mux_conn[0]
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use conn1 as mux_conn[1]
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use conn2 as mux_conn[2]
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use conn3 as mux_conn[3]
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device pnp 0c09.0 on end
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end
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end
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device ref pmc hidden
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chip drivers/intel/pmc_mux
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device generic 0 on
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chip drivers/intel/pmc_mux/conn
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#USB2_C0
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use usb2_port2 as usb2_port
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use tcss_usb3_port0 as usb3_port
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device generic 0 alias conn0 on end
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end
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chip drivers/intel/pmc_mux/conn
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#USB2_C1
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use usb2_port3 as usb2_port
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use tcss_usb3_port2 as usb3_port
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device generic 1 alias conn1 on end
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end
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chip drivers/intel/pmc_mux/conn
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#USB2_C2
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use usb2_port1 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 2 alias conn2 on end
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end
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chip drivers/intel/pmc_mux/conn
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#USB2_C3
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use usb2_port5 as usb2_port
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use tcss_usb3_port1 as usb3_port
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device generic 3 alias conn3 on end
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end
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end
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end
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end
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end
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end
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