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mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization error 

Configure eMMC DLL tuning values for Pujjo board Kioxia sku.

BUG=b:261676386
TEST=Use the value to boot on Pujjo successfully.

Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I46991f26571771620dcd94b90e1112484ade63bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Leo Chou 2022-12-20 15:28:31 +08:00 committed by Eric Lai
parent 0d76a30767
commit a86af49b9d
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/google/brya/variants/pujjo/overridetree.cb
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@ -75,7 +75,7 @@ chip soc/intel/alderlake
# [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78. # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
# [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119. # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
# [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119. # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1D1B" register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B4F1B"
# EMMC RX CMD/DATA Delay 2 # EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-42.3.12. # Refer to EDS-Vol2-42.3.12.
@ -86,7 +86,7 @@ chip soc/intel/alderlake
# 11: Reserved # 11: Reserved
# [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39. # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
# [6:0] steps of delay for HS200, each 125ps, range: 0 - 79. # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10049" register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10023"
# EMMC Rx Strobe Delay # EMMC Rx Strobe Delay
# Refer to EDS-Vol2-42.3.11. # Refer to EDS-Vol2-42.3.11.