google/cyan: set touchscreen GPIO to non_maskable

Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...]
in additon to changing the touchpad/touchscreen interrupts from
edge to level triggered, also marked them as maskable. This not only
broke the touchpad functionality, but caused issues with the touchpad
as well.  Revert the touchpad to being non_maskable for all cyan
variants with a touchscreen.

Test: boot GalliumOS on google/cyan with a range of kernel versions
(4.15.18, 4.16.13, 4.17.x, 4.18.x) and verify touchscreen functional,
touchpad working properly (not jittery)

Change-Id: I0e0357912f9404af7d0f4e7938a1a94c74810b37
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Matt DeVillier 2018-08-27 17:04:53 -05:00 committed by Patrick Georgi
parent 58363b4a3b
commit a86bbea04d
9 changed files with 9 additions and 9 deletions

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@ -163,7 +163,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -164,7 +164,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */
GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPIO_NC, GPIO_NC,
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */

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@ -166,7 +166,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -163,7 +163,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -165,7 +165,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -166,7 +166,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -164,7 +164,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -165,7 +165,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 21 SEC_GPIO_SUS11 */

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@ -164,7 +164,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = {
/* 17 GPIO_SUS3 */ /* 17 GPIO_SUS3 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA),
/* 18 GPIO_SUS7 */ /* 18 GPIO_SUS7 */
GPI(trig_level_low, L1, P_1K_H, 0, NA, UNMASK_WAKE, NA), GPI(trig_level_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),
/* 19 GPIO_SUS1 */ /* 19 GPIO_SUS1 */
GPIO_NC, /* 20 GPIO_SUS5 */ GPIO_NC, /* 20 GPIO_SUS5 */
GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */ GPIO_INPUT_NO_PULL, /* 21 SEC_GPIO_SUS11 */