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mb/gigabyte/ga-h61m-s2pv: fix cosmetic things

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Remove unneeded options, note where usbdebug is, reorder devicetree and
clean up dsdt.

Tested, board still boots.

Change-Id: Ice0eff7b9829816aff4d334f4ac4a2fb435a2fb0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons 2019-02-24 19:54:15 +01:00 committed by Nico Huber
parent f8f2e8c39e
commit a86e401c0e
3 changed files with 12 additions and 24 deletions
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10
src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig
View file

@ -40,14 +40,6 @@ config MAINBOARD_PART_NUMBER
string string
default "GA-H61M-S2PV" default "GA-H61M-S2PV"
config VGA_BIOS_FILE
string
default "pci8086,0102.rom"
config VGA_BIOS_ID
string
default "8086,0102"
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex hex
default 0x5001 default 0x5001
@ -60,7 +52,7 @@ config MAX_CPUS
int int
default 8 default 8
config USBDEBUG_HCD_INDEX # FIXME: check this config USBDEBUG_HCD_INDEX # Bottom left port seen from rear
int int
default 2 default 2

9
src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb
View file

@ -30,12 +30,12 @@ chip northbridge/intel/sandybridge
end end
register "pci_mmio_size" = "2048" register "pci_mmio_size" = "2048"
device domain 0x0 on device domain 0x0 on
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16)
device pci 02.0 on end # Internal graphics VGA controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065" register "c2_latency" = "0x0065"
register "docking_supported" = "0"
register "gen1_dec" = "0x003c0a01" register "gen1_dec" = "0x003c0a01"
register "p_cnt_throttling_supported" = "0"
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1" register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3" register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"
@ -100,8 +100,5 @@ chip northbridge/intel/sandybridge
device pci 1f.5 off end # SATA Controller 2 device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 off end # Thermal device pci 1f.6 off end # Thermal
end end
device pci 00.0 on end # Host bridge
device pci 01.0 on end # PCIe Bridge for discrete graphics (PCIEX16)
device pci 02.0 on end # Internal graphics VGA controller
end end
end end

7
src/mainboard/gigabyte/ga-h61m-s2pv/dsdt.asl
View file

@ -14,7 +14,9 @@
*/ */
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#include <arch/acpi.h> #include <arch/acpi.h>
DefinitionBlock( DefinitionBlock(
"dsdt.aml", "dsdt.aml",
"DSDT", "DSDT",
@ -24,7 +26,6 @@ DefinitionBlock(
0x20141018 // OEM revision 0x20141018 // OEM revision
) )
{ {
// Some generic macros
#include "acpi/mainboard.asl" #include "acpi/mainboard.asl"
#include "acpi/platform.asl" #include "acpi/platform.asl"
#include "acpi/superio.asl" #include "acpi/superio.asl"
@ -36,12 +37,10 @@ DefinitionBlock(
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
Scope (\_SB) { Device (\_SB.PCI0)
Device (PCI0)
{ {
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
#include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
#include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl>
} }
}
} }