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soc/intel/cannonlake: CannonaLake make use of FVI information 

Select DISPLAY_FSP_VERSION_INFO Kconfig to get all required
firmware information right after FSP-S.

TEST=Display FW information as below

>> Display FSP Version Info HOB
Reference Code - CPU = 7.1.20.52
uCode Version = 0.0.0.16
Reference Code - ME 11.0 = 7.1.20.52
MEBx version = 0.0.0.0
ME Firmware Version = Consumer SKU
Reference Code - CNL PCH = 7.1.20.52
PCH-CRID Status = Disabled
CNL PCH H A0 Hsio Version = 2.0.0.0
CNL PCH H Ax Hsio Version = 9.0.0.0
CNL PCH H Bx Hsio Version = 5.0.0.0
CNL PCH LP Ax Hsio Version = 13.0.0.0
CNL PCH LP B0 Hsio Version = 7.0.0.0
CNL PCH LP Bx Hsio Version = 6.0.0.0
CNL PCH LP Dx Hsio Version = 2.0.0.0
Reference Code - SA - System Agent = 7.1.20.52
Reference Code - MRC = 0.5.1.19
SA - PCIe Version = 7.1.20.52
SA-CRID Status = Disabled
SA-CRID Original Value = 0.0.0.0
SA-CRID New Value = 0.0.0.0

Change-Id: Ibfcac0002998e8a6594bb6dfc68b2577f62ddbff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23387
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2018-01-23 16:40:56 +05:30
parent 73b67dcee8
commit a8733e381d
2 changed files with 4 additions and 0 deletions
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1
src/soc/intel/cannonlake/Kconfig
View File

@ -76,6 +76,7 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_2017_BINDING
select DISPLAY_FSP_VERSION_INFO
config UART_DEBUG
bool "Enable UART debug port."

3
src/soc/intel/cannonlake/chip.c
View File

@ -132,6 +132,9 @@ void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
}
static void pci_domain_set_resources(device_t dev)