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haswell/broadwell: Replace remaining MCHBAR accessors 

Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 and Purism Librem 13 v1
remain identical.

Change-Id: I74b633fb0b012304b5b4bd943272ed82dcb6f7d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52468
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2021-04-17 14:34:37 +02:00
parent cf730ce481
commit a8753e9cbb
7 changed files with 34 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/haswell/raminit.c
View File

@ -174,7 +174,7 @@ static void sdram_initialize(struct pei_data *pei_data)
* Ensure the mc_init_done_ack bit is set before continuing. Otherwise,
* attempting to access memory will lock up the system.
*/
if (!(MCHBAR32(MC_INIT_STATE_G) & (1 << 5))) {
if (!(mchbar_read32(MC_INIT_STATE_G) & (1 << 5))) {
printk(BIOS_EMERG, "Memory controller did not acknowledge raminit.\n");
die("MRC raminit failed\n");
}

12
src/soc/intel/broadwell/acpi.c
View File

@ -29,16 +29,16 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static unsigned long acpi_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1;
const u32 gfxvtbar = mchbar_read32(GFXVTBAR) & ~0xfff;
const u32 vtvc0bar = mchbar_read32(VTVC0BAR) & ~0xfff;
const bool gfxvten = mchbar_read32(GFXVTBAR) & 0x1;
const bool vtvc0en = mchbar_read32(VTVC0BAR) & 0x1;
/* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */
const bool emit_igd =
igfx_dev && igfx_dev->enabled &&
gfxvtbar && gfxvten &&
!MCHBAR32(GFXVTBAR + 4);
!mchbar_read32(GFXVTBAR + 4);
/* First, add DRHD entries */
if (emit_igd) {
@ -51,7 +51,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
}
/* VTVC0BAR has to be set, enabled, and in 32-bit space */
if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) {
if (vtvc0bar && vtvc0en && !mchbar_read32(VTVC0BAR + 4)) {
const unsigned long tmp = current;
current += acpi_create_dmar_drhd(current,
DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);

12
src/soc/intel/broadwell/early_init.c
View File

@ -15,8 +15,8 @@ static void broadwell_setup_bars(void)
pci_write_config32(SA_DEV_ROOT, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1);
pci_write_config32(SA_DEV_ROOT, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1);
MCHBAR32(EDRAMBAR) = EDRAM_BASE_ADDRESS | 1;
MCHBAR32(GDXCBAR) = GDXC_BASE_ADDRESS | 1;
mchbar_write32(EDRAMBAR, EDRAM_BASE_ADDRESS | 1);
mchbar_write32(GDXCBAR, GDXC_BASE_ADDRESS | 1);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(SA_DEV_ROOT, PAM0, 0x30);
@ -40,10 +40,10 @@ void systemagent_early_init(void)
if (vtd_capable) {
/* setup BARs: zeroize top 32 bits; set enable bit */
MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32;
MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32;
MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
/* set PRSCAPDIS, lock GFXVTBAR policy cfg registers */
u32 reg32;

24
src/soc/intel/broadwell/finalize.c
View File

@ -33,20 +33,20 @@ static void broadwell_systemagent_finalize(void)
pci_or_config32(host_bridge, TSEG, 1 << 0);
pci_or_config32(host_bridge, TOLUD, 1 << 0);
MCHBAR32(0x50fc) |= 0x8f; /* MC */
MCHBAR32(0x5500) |= 1 << 0; /* PAVP */
MCHBAR32(0x5880) |= 1 << 5; /* DDR PTM */
MCHBAR32(0x7000) |= 1 << 31;
MCHBAR32(0x77fc) |= 1 << 0;
MCHBAR32(0x7ffc) |= 1 << 0;
MCHBAR32(0x6800) |= 1 << 31;
MCHBAR32(0x6020) |= 1 << 0; /* UMA GFX */
MCHBAR32(0x63fc) |= 1 << 0; /* VTDTRK */
mchbar_setbits32(0x50fc, 0x8f); /* MC */
mchbar_setbits32(0x5500, 1 << 0); /* PAVP */
mchbar_setbits32(0x5880, 1 << 5); /* DDR PTM */
mchbar_setbits32(0x7000, 1 << 31);
mchbar_setbits32(0x77fc, 1 << 0);
mchbar_setbits32(0x7ffc, 1 << 0);
mchbar_setbits32(0x6800, 1 << 31);
mchbar_setbits32(0x6020, 1 << 0); /* UMA GFX */
mchbar_setbits32(0x63fc, 1 << 0); /* VTDTRK */
/* Read+write the following */
MCHBAR32(0x6030) = MCHBAR32(0x6030);
MCHBAR32(0x6034) = MCHBAR32(0x6034);
MCHBAR32(0x6008) = MCHBAR32(0x6008);
mchbar_setbits32(0x6030, 0);
mchbar_setbits32(0x6034, 0);
mchbar_setbits32(0x6008, 0);
}
static void broadwell_finalize(void *unused)

2
src/soc/intel/broadwell/gma.c
View File

@ -529,7 +529,7 @@ static void igd_init(struct device *dev)
}
/* Set RP1 graphics frequency */
rp1_gfx_freq = (MCHBAR32(0x5998) >> 8) & 0xff;
rp1_gfx_freq = (mchbar_read32(0x5998) >> 8) & 0xff;
gtt_write(0xa008, rp1_gfx_freq << 24);
/* Post VBIOS panel setup */

15
src/soc/intel/broadwell/northbridge.c
View File

@ -93,7 +93,7 @@ static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base,
{
u32 bar;
bar = MCHBAR32(index);
bar = mchbar_read32(index);
/* If not enabled don't report it. */
if (!(bar & 0x1))
@ -400,21 +400,14 @@ static void systemagent_read_resources(struct device *dev)
static void systemagent_init(struct device *dev)
{
u8 bios_reset_cpl, pair;
/* Enable Power Aware Interrupt Routing */
pair = MCHBAR8(MCH_PAIR);
pair &= ~0x7; /* Clear 2:0 */
pair |= 0x4; /* Fixed Priority */
MCHBAR8(MCH_PAIR) = pair;
/* Enable Power Aware Interrupt Routing. */
mchbar_clrsetbits8(MCH_PAIR, 0x7, 0x4); /* Clear 2:0, set Fixed Priority */
/*
* Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialized memory and power management
*/
bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
bios_reset_cpl |= 3;
MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
mchbar_setbits8(BIOS_RESET_CPL, 3);
printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
/* Configure turbo power limits 1ms after reset complete bit */

8
src/soc/intel/broadwell/raminit.c
View File

@ -42,10 +42,10 @@ static void report_memory_config(void)
{
int i;
const u32 addr_decoder_common = MCHBAR32(MAD_CHNL);
const u32 addr_decoder_common = mchbar_read32(MAD_CHNL);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
(mchbar_read32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
(addr_decoder_common >> 0) & 3,
@ -53,7 +53,7 @@ static void report_memory_config(void)
(addr_decoder_common >> 4) & 3);
for (i = 0; i < NUM_CHANNELS; i++) {
const u32 ch_conf = MCHBAR32(MAD_DIMM(i));
const u32 ch_conf = mchbar_read32(MAD_DIMM(i));
printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf);
printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]);
@ -129,7 +129,7 @@ void sdram_initialize(struct pei_data *pei_data)
die("pei_data version mismatch\n");
/* Print the MRC version after executing the UEFI PEI stage. */
u32 version = MCHBAR32(MRC_REVISION);
u32 version = mchbar_read32(MRC_REVISION);
printk(BIOS_DEBUG, "MRC Version %d.%d.%d Build %d\n",
(version >> 24) & 0xff, (version >> 16) & 0xff,
(version >> 8) & 0xff, (version >> 0) & 0xff);