From a8754bd2a362071ef8db21907beb8d7040eb71e1 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@scarletltd.com>
Date: Sun, 18 Jun 2017 17:35:27 -0600
Subject: [PATCH] google/kahlee: Add EC and GNVS ACPI

Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.

Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/google/kahlee/dsdt.asl | 17 +++++++++++++++++
 src/mainboard/google/kahlee/ec.c     |  1 +
 src/mainboard/google/kahlee/ec.h     |  9 ++++++++-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 6c53481d1b..3f91c7a4a9 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -13,6 +13,8 @@
  * GNU General Public License for more details.
  */
 
+#include "ec.h"
+
 /* DefinitionBlock Statement */
 DefinitionBlock (
 	"DSDT.AML",	/* Output filename */
@@ -25,6 +27,9 @@ DefinitionBlock (
 {	/* Start of ASL file */
 	/* #include <arch/x86/acpi/debug.asl> */	/* as needed */
 
+	/* global NVS and variables */
+	#include <globalnvs.asl>
+
 	/* Globals for the platform */
 	#include "acpi/mainboard.asl"
 
@@ -74,6 +79,18 @@ DefinitionBlock (
 
 	} /* End \_SB scope */
 
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	/* Chrome OS Embedded Controller */
+	Scope (\_SB.PCI0.LPCB)
+	{
+		/* ACPI code for EC SuperIO functions */
+		#include <ec/google/chromeec/acpi/superio.asl>
+		/* ACPI code for EC functions */
+		#include <ec/google/chromeec/acpi/ec.asl>
+	}
+
 	/* Describe SMBUS for the Southbridge */
 	#include <smbus.asl>
 
diff --git a/src/mainboard/google/kahlee/ec.c b/src/mainboard/google/kahlee/ec.c
index da0f855331..71c6e1023c 100644
--- a/src/mainboard/google/kahlee/ec.c
+++ b/src/mainboard/google/kahlee/ec.c
@@ -15,6 +15,7 @@
 
 #include <arch/acpi.h>
 #include <console/console.h>
+#include <ec/google/chromeec/ec.h>
 #include "ec.h"
 #include <rules.h>
 #include <soc/hudson.h>
diff --git a/src/mainboard/google/kahlee/ec.h b/src/mainboard/google/kahlee/ec.h
index 5b7740bbee..b8b5af802a 100644
--- a/src/mainboard/google/kahlee/ec.h
+++ b/src/mainboard/google/kahlee/ec.h
@@ -17,7 +17,6 @@
 #define MAINBOARD_EC_H
 
 #include <ec/ec.h>
-#include <ec/google/chromeec/ec.h>
 #include <ec/google/chromeec/ec_commands.h>
 
 /* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
@@ -59,4 +58,12 @@
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
 	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
 
+/* Enable LID switch */
+#define EC_ENABLE_LID_SWITCH
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K	/* Enable PS/2 Keyboard */
+#define SIO_EC_ENABLE_COM1	/* Enable Serial Port 1 */
+
 #endif