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cezanne/psp_verstage: update SRAM address 

Loading address and size for the user app has been changed with recent
PSP release.

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kangheui Won 2021-05-07 17:12:41 +10:00 committed by Martin Roth
parent dad067f272
commit a8779941dc
1 changed files with 4 additions and 4 deletions
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8
src/soc/amd/cezanne/include/soc/psp_verstage_addr.h
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@ -8,8 +8,8 @@
* header for the user app (verstage) must be mapped. * header for the user app (verstage) must be mapped.
* Size is 0x14000 bytes * Size is 0x14000 bytes
*/ */
#define PSP_SRAM_START 0x36000 #define PSP_SRAM_START 0x26000
#define PSP_SRAM_SIZE (80K) #define PSP_SRAM_SIZE (148K)
#define VERSTAGE_START PSP_SRAM_START #define VERSTAGE_START PSP_SRAM_START
/* /*
@ -17,7 +17,7 @@
* and make the size a multiple of 4k * and make the size a multiple of 4k
*/ */
#define PSP_VERSTAGE_STACK_START 0x49000 #define PSP_VERSTAGE_STACK_START 0x41000
#define PSP_VERSTAGE_STACK_SIZE (4K) #define PSP_VERSTAGE_STACK_SIZE (40K)
#endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */ #endif /* AMD_CEZANNE_PSP_VERSTAGE_ADDR_H */