mainboard/amd/bimini_fam10: Use C89 comments style & remove commented code
Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
874fe1d328
commit
a8802577ea
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@ -63,22 +63,11 @@ void enable_int_gfx(void)
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void set_pcie_dereset(void)
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{
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/* GPIO 50h reset PCIe slot */
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/*
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u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
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u8 byte = ~(1 << 5);
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byte |= ~(1 << 6);
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*addr = byte;
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*/
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}
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void set_pcie_reset(void)
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{
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/* GPIO 50h reset PCIe slot */
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/*
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u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
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u8 byte = ~((1 << 5) | (1 << 6));
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*addr = byte;
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*/
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}
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u8 is_dev3_present(void)
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@ -86,34 +75,6 @@ u8 is_dev3_present(void)
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return 0;
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}
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#if 0 /* not tested yet. */
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/********************************************************
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* bimini uses SB800 GPIO9 to detect IDE_DMA66.
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* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
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* get the cable type, 40 pin or 80 pin?
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********************************************************/
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static void get_ide_dma66(void)
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{
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u8 byte;
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/*u32 sm_dev, ide_dev; */
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device_t sm_dev, ide_dev;
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0xA9);
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byte |= (1 << 5); /* Set Gpio9 as input */
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pci_write_config8(sm_dev, 0xA9, byte);
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ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
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byte = pci_read_config8(ide_dev, 0x56);
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byte &= ~(7 << 0);
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if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
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byte |= 2 << 0; /* mode 2 */
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else
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byte |= 5 << 0; /* mode 5 */
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pci_write_config8(ide_dev, 0x56, byte);
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}
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#endif /* get_ide_dma66() */
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/*************************************************
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* enable the dedicated function in bimini board.
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@ -125,7 +86,6 @@ static void mainboard_enable(device_t dev)
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set_pcie_dereset();
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enable_int_gfx();
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/* get_ide_dma66(); */
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}
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struct chip_operations mainboard_ops = {
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@ -43,7 +43,7 @@ static void setup_mb_resource_map(void)
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* This field defines the upper address bits of a 40 bit address
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* that define the end of the DRAM region.
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
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/* Don't touch it, we need it for CONFIG_CAR_FAM10 */
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
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@ -81,7 +81,8 @@ static void setup_mb_resource_map(void)
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* This field defines the upper address bits of a 40-bit address
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* that define the start of the DRAM region.
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
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/* don't touch it, we need it for CONFIG_CAR_FAM10 */
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
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@ -129,7 +130,6 @@ static void setup_mb_resource_map(void)
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
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/* Memory-Mapped I/O Base i Registers
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* F1:0x80 i = 0
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@ -164,7 +164,6 @@ static void setup_mb_resource_map(void)
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
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/* PCI I/O Limit i Registers
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* F1:0xC4 i = 0
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@ -191,7 +190,6 @@ static void setup_mb_resource_map(void)
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* This field defines the end of PCI I/O region n
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* [31:25] Reserved
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
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@ -221,7 +219,6 @@ static void setup_mb_resource_map(void)
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* This field defines the start of PCI I/O region n
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* [31:25] Reserved
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
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@ -262,7 +259,7 @@ static void setup_mb_resource_map(void)
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* [31:24] Bus Number Limit i
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* This field defines the highest bus number in configuration regin i
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*/
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// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
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/* AMD 8111 on link0 of CPU 0 */
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
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PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
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@ -13,11 +13,9 @@
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* GNU General Public License for more details.
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*/
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//#define SYSTEM_TYPE 0 /* SERVER */
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#define SYSTEM_TYPE 1 /* DESKTOP */
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//#define SYSTEM_TYPE 2 /* MOBILE */
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#define SYSTEM_TYPE 1 /* SERVER = 0, DESKTOP = 1, MOBILE = 2 */
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//used by incoherent_ht
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/* used by incoherent_ht */
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#define FAM10_SCAN_PCI_BUS 0
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#define FAM10_ALLOCATE_IO_RANGE 0
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@ -100,12 +98,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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console_init();
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// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
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/* Halt if there was a built in self test failure */
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report_bist_failure(bist);
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// Load MPB
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/* Load MPB */
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val = cpuid_eax(1);
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printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
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printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
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@ -164,10 +161,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x39);
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if (!warm_reset_detect(0)) { // BSP is node 0
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if (!warm_reset_detect(0)) { /* BSP is node 0 */
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init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
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} else {
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init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
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init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
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}
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post_code(0x3A);
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@ -194,8 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x40);
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// die("Die Before MCT init.");
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timestamp_add_now(TS_BEFORE_INITRAM);
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printk(BIOS_DEBUG, "raminit_amdmct()\n");
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raminit_amdmct(sysinfo);
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@ -206,24 +201,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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amdmct_cbmem_store_info(sysinfo);
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/*
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dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
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dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
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dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
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dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
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*/
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// ram_check(0x00200000, 0x00200000 + (640 * 1024));
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// ram_check(0x40200000, 0x40200000 + (640 * 1024));
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// die("After MCT init before CAR disabled.");
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rs780_before_pci_init();
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sb800_before_pci_init();
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post_code(0x42);
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post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
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post_code(0x43); // Should never see this post code.
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post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
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post_code(0x43); /* Should never see this post code. */
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}
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/**
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