mainboard/amd/bimini_fam10: Use C89 comments style & remove commented code

Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/amd/bimini_fam10/mainboard.c

@@ -63,22 +63,11 @@ void enable_int_gfx(void)
 void set_pcie_dereset(void)
 {
 	/* GPIO 50h reset PCIe slot */
-/*
-	u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
-	u8 byte = ~(1 << 5);
-	byte |= ~(1 << 6);
-	*addr = byte;
-*/
 }
 
 void set_pcie_reset(void)
 {
 	/* GPIO 50h reset PCIe slot */
-/*
-	u8 *addr = (u8 *)(0xFED80000 + 0x100 + 0x50);
-	u8 byte = ~((1 << 5) | (1 << 6));
-	*addr = byte;
-*/
 }
 
 u8 is_dev3_present(void)
@@ -86,34 +75,6 @@ u8 is_dev3_present(void)
 	return 0;
 }
 
-#if 0	     /* not tested yet. */
-/********************************************************
-* bimini uses SB800 GPIO9 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
-* get the cable type, 40 pin or 80 pin?
-********************************************************/
-static void get_ide_dma66(void)
-{
-	u8 byte;
-	/*u32 sm_dev, ide_dev; */
-	device_t sm_dev, ide_dev;
-
-	sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
-
-	byte = pci_read_config8(sm_dev, 0xA9);
-	byte |= (1 << 5);	/* Set Gpio9 as input */
-	pci_write_config8(sm_dev, 0xA9, byte);
-
-	ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
-	byte = pci_read_config8(ide_dev, 0x56);
-	byte &= ~(7 << 0);
-	if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
-		byte |= 2 << 0;	/* mode 2 */
-	else
-		byte |= 5 << 0;	/* mode 5 */
-	pci_write_config8(ide_dev, 0x56, byte);
-}
-#endif	/* get_ide_dma66() */
 
 /*************************************************
 * enable the dedicated function in bimini board.
@@ -125,7 +86,6 @@ static void mainboard_enable(device_t dev)
 
 	set_pcie_dereset();
 	enable_int_gfx();
-	/* get_ide_dma66(); */
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/amd/bimini_fam10/resourcemap.c

@@ -43,7 +43,7 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40 bit  address
 		 *	   that define the end of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+		/* Don't touch it, we need it for CONFIG_CAR_FAM10 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -81,7 +81,8 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the upper address bits of a 40-bit address
 		 *	   that define the start of the DRAM region.
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+
+		/* don't touch it, we need it for CONFIG_CAR_FAM10 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -129,7 +130,6 @@ static void setup_mb_resource_map(void)
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
 
 		/* Memory-Mapped I/O Base i Registers
 		 * F1:0x80 i = 0
@@ -164,7 +164,6 @@ static void setup_mb_resource_map(void)
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
 
 		/* PCI I/O Limit i Registers
 		 * F1:0xC4 i = 0
@@ -191,7 +190,6 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the end of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -221,7 +219,6 @@ static void setup_mb_resource_map(void)
 		 *	   This field defines the start of PCI I/O region n
 		 * [31:25] Reserved
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -262,7 +259,7 @@ static void setup_mb_resource_map(void)
 		 * [31:24] Bus Number Limit i
 		 *	   This field defines the highest bus number in configuration regin i
 		 */
-//		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+		/* AMD 8111 on link0 of CPU 0 */
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
 		PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,

src/mainboard/amd/bimini_fam10/romstage.c

@@ -13,11 +13,9 @@
  * GNU General Public License for more details.
  */
 
-//#define SYSTEM_TYPE 0	/* SERVER */
+#define SYSTEM_TYPE 1	/* SERVER = 0, DESKTOP = 1, MOBILE = 2 */
-#define SYSTEM_TYPE 1	/* DESKTOP */
-//#define SYSTEM_TYPE 2	/* MOBILE */
 
-//used by incoherent_ht
+/* used by incoherent_ht */
 #define FAM10_SCAN_PCI_BUS 0
 #define FAM10_ALLOCATE_IO_RANGE 0
 
@@ -100,12 +98,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	console_init();
 
-//	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
 
 	/* Halt if there was a built in self test failure */
 	report_bist_failure(bist);
 
-	// Load MPB
+	/* Load MPB */
 	val = cpuid_eax(1);
 	printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
 	printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -164,10 +161,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x39);
 
-	if (!warm_reset_detect(0)) {			// BSP is node 0
+	if (!warm_reset_detect(0)) {			/* BSP is node 0 */
 		init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
 	} else {
-		init_fidvid_stage2(bsp_apicid, 0);	// BSP is node 0
+		init_fidvid_stage2(bsp_apicid, 0);	/* BSP is node 0 */
 	}
 
 	post_code(0x3A);
@@ -194,8 +191,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	post_code(0x40);
 
-//	die("Die Before MCT init.");
-
 	timestamp_add_now(TS_BEFORE_INITRAM);
 	printk(BIOS_DEBUG, "raminit_amdmct()\n");
 	raminit_amdmct(sysinfo);
@@ -206,24 +201,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 	amdmct_cbmem_store_info(sysinfo);
 
-/*
-	dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
-	dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
-	dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
-	dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-//	ram_check(0x00200000, 0x00200000 + (640 * 1024));
-//	ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-//	die("After MCT init before CAR disabled.");
-
 	rs780_before_pci_init();
 	sb800_before_pci_init();
 
 	post_code(0x42);
-	post_cache_as_ram();	// BSP switch stack to ram, copy then execute LB.
+	post_cache_as_ram();	/* BSP switch stack to ram, copy then execute LB. */
-	post_code(0x43);	// Should never see this post code.
+	post_code(0x43);	/* Should never see this post code. */
 }
 
 /**