mb/intel/mtlrvp: Enable GSPI interface

This patch enables GSPI [1] interface for mtlrvp based on mtlrvp
schematics.

BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223)
SPI[0].Mode                 = 0
SPI[0].DefaultCsOutput      = 0
SPI[0].CsMode               = 0
SPI[0].CsState              = 0
SPI[1].Mode                 = 1
SPI[1].DefaultCsOutput      = 0
SPI[1].CsMode               = 0
SPI[1].CsState              = 0

Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>

src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb

@@ -69,6 +69,21 @@ chip soc/intel/meteorlake
 		},
 	}"
 
+	register "serial_io_gspi_mode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+	}"
+
+	register "serial_io_gspi_cs_mode" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
+	register "serial_io_gspi_cs_state" = "{
+		[PchSerialIoIndexGSPI0] = 0,
+		[PchSerialIoIndexGSPI1] = 0,
+	}"
+
 	device domain 0 on
 		device ref igpu on end
 		device ref heci1 on end
@@ -129,6 +144,7 @@ chip soc/intel/meteorlake
 		device ref i2c5 on end
 		device ref shared_sram on end
 		device ref uart0 on end
+		device ref gspi1 on end
 		device ref smbus on end
 	end
 end