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purism/librem13v2: Fix USB settings and set OC pin 

The USB settings were wrong in some places, or missing and the
USB_OC values were taken from the schematics.

Change-Id: I29b564a4161c486f5e8556b1726471bfa2351b7a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/22043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Youness Alaoui 2017-07-25 14:11:31 -04:00 committed by Martin Roth
parent c5b9658961
commit a8b35be75e
1 changed files with 7 additions and 4 deletions
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11
src/mainboard/purism/librem13v2/devicetree.cb
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@ -154,14 +154,17 @@ chip soc/intel/skylake
register "PcieRpEnable[4]" = "1"
register "PcieRpEnable[8]" = "1"
register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (right)
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port (right)
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port (left)
register "usb2_ports[5]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # SD
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port (right)
# OC1 should be for Type-C but it seems to not have been wired, according to
# the available schematics, even though it is labeled as USB_OC_TYPEC.
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port (right)
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
# PL2 override 25W