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southbridge/amd/sr5650: Hide clock configuration device after setup is complete 

Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12045
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Timothy Pearson 2015-08-13 17:45:12 -05:00 committed by Martin Roth
parent 44e4a4e4db
commit a8c6c7f30c
2 changed files with 11 additions and 8 deletions
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16
src/southbridge/amd/sr5650/early_setup.c
View File

@ -410,14 +410,14 @@ static void sr5650_por_misc_index_init(device_t nb_dev)
set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310);
/* NBCFG (NBMISCIND 0x0): NB_CNTL -
* HIDE_NB_AGP_CAP ([0], default=1)HIDE
* HIDE_P2P_AGP_CAP ([1], default=1)HIDE
* HIDE_NB_GART_BAR ([2], default=1)HIDE
* HIDE_MMCFG_BAR ([3], default=1)SHOW
* AGPMODE30 ([4], default=0)DISABLE
* AGP30ENCHANCED ([5], default=0)DISABLE
* HIDE_AGP_CAP ([8], default=1)ENABLE */
set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6);
* HIDE_NB_AGP_CAP ([0], default=1)HIDE
* HIDE_P2P_AGP_CAP ([1], default=1)HIDE
* HIDE_NB_GART_BAR ([2], default=1)HIDE
* HIDE_MMCFG_BAR ([3], default=1)SHOW
* AGPMODE30 ([4], default=0)DISABLE
* AGP30ENCHANCED ([5], default=0)DISABLE
* HIDE_CLKCFG_HEADER ([8], default=0)SHOW */
set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8);
/* IOC_LAT_PERF_CNTR_CNTL */
set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00);

3
src/southbridge/amd/sr5650/pcie.c
View File

@ -850,6 +850,9 @@ void sr56x0_lock_hwinitreg(void)
/* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */
set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7);
/* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */
set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8);
}
/*****************************************