mb/amd/chausie: add mainboard as copy of mb/amd/majolica

To have the new AMD Sabrina SoC code tested, add the AMD Chausie
mainboard as a copy of Majolica. This patch also changes the name from
Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC
and comments out the APCB_SOURCES since those aren't available in the
3rdparty/blobs repository yet.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/mainboard/amd/chausie/Kconfig

@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_AMD_CHAUSIE
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select HAVE_ACPI_RESUME
+	select SOC_AMD_SABRINA
+	select SOC_AMD_COMMON_BLOCK_USE_ESPI
+	select AMD_SOC_CONSOLE_UART
+	select MAINBOARD_HAS_CHROMEOS
+
+config FMDFILE
+	default "src/mainboard/amd/chausie/chromeos.fmd" if CHROMEOS
+	default "src/mainboard/amd/chausie/board.fmd"
+
+config MAINBOARD_DIR
+	default "amd/chausie"
+
+config MAINBOARD_PART_NUMBER
+	default "CHAUSIE"
+
+config AMD_FWM_POSITION_INDEX
+	int
+	default 3 if CHROMEOS
+	default 4
+	help
+	  TODO: might need to be adapted for better placement of files in cbfs
+
+config CHAUSIE_HAVE_MCHP_FW
+	bool "Have Microchip EC firmware?"
+	default n
+
+config CHAUSIE_MCHP_FW_FILE
+	string
+	depends on CHAUSIE_HAVE_MCHP_FW
+	default "3rdparty/blobs/mainboard/amd/chausie/EC_chausie.bin"
+	help
+	  The EC firmware blob is usually the first 128kByte of the stock
+	  firmware image.
+
+config VBOOT
+	select VBOOT_NO_BOARD_SUPPORT
+	select VBOOT_SEPARATE_VERSTAGE
+	select VBOOT_STARTS_IN_BOOTBLOCK
+
+config VBOOT_VBNV_OFFSET
+	hex
+	default 0x2A
+
+config CHROMEOS
+	# Use default libpayload config
+	select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE
+
+if !EM100	# EM100 defaults in soc/amd/common/blocks/spi/Kconfig
+config EFS_SPI_READ_MODE
+	default 3	# Quad IO (1-1-4)
+
+config EFS_SPI_SPEED
+	default 0	# 66MHz
+
+config EFS_SPI_MICRON_FLAG
+	default 0
+
+config NORMAL_READ_SPI_SPEED
+	default 1	# 33MHz
+
+config ALT_SPI_SPEED
+	default 1	# 33MHz
+
+config TPM_SPI_SPEED
+	default 1	# 33MHz
+
+endif # !EM100
+
+endif # BOARD_AMD_CHAUSIE

src/mainboard/amd/chausie/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_AMD_CHAUSIE
+	bool "Chausie"

src/mainboard/amd/chausie/Makefile.inc

@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-y += early_gpio.c
+
+romstage-y += port_descriptors.c
+
+ramstage-y += chromeos.c
+
+#TODO: add APCB binaries
+#APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin
+#APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin
+
+ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y)
+$(call add_intermediate, add_mchp_fw)
+	$(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_CHAUSIE_MCHP_FW_FILE) --fill-upward
+else
+files_added:: warn_no_mchp
+endif # CONFIG_CHAUSIE_HAVE_MCHP_FW
+
+PHONY+=warn_no_mchp
+warn_no_mchp:
+	printf "\n\t** WARNING **\n"
+	printf "coreboot has been built without the Microchip EC FW.\n"
+	printf "Do not flash this image.  Your Chausie's power button\n"
+	printf "will not respond when you press it.\n\n"

src/mainboard/amd/chausie/board.fmd

@@ -0,0 +1,8 @@
+FLASH@0xFF000000 16M {
+	BIOS {
+		EC 128K
+		RW_MRC_CACHE 64K
+		FMAP 4K
+		COREBOOT(CBFS)
+	}
+}

src/mainboard/amd/chausie/board_info.txt

@@ -0,0 +1 @@
+Category: eval

src/mainboard/amd/chausie/bootblock.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include "gpio.h"
+
+void bootblock_mainboard_early_init(void)
+{
+	mainboard_program_early_gpios();
+}

src/mainboard/amd/chausie/chromeos.c

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootmode.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <types.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+	/* Chausie doesn't have a write protect pin */
+	return 0;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	/* No ChromeOS GPIOs */
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/amd/chausie/chromeos.fmd

@@ -0,0 +1,34 @@
+FLASH@0xFF000000 16M {
+	SI_BIOS {
+		EC 128K
+		RW_MRC_CACHE(PRESERVE) 64K
+		RW_SECTION_A 3M {
+			VBLOCK_A 8K
+			FW_MAIN_A(CBFS)
+			RW_FWID_A 256
+		}
+		RW_SECTION_B 3M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 256
+		}
+		RW_ELOG(PRESERVE) 4K
+		RW_SHARED 16K {
+			SHARED_DATA 8K
+			VBLOCK_DEV 8K
+		}
+		RW_VPD(PRESERVE) 8K
+		RW_NVRAM(PRESERVE) 20K
+		SMMSTORE(PRESERVE) 4K
+		RW_LEGACY(CBFS)
+		WP_RO@8M 8M {
+			RO_VPD(PRESERVE) 16K
+			RO_SECTION {
+				FMAP 2K
+				RO_FRID 64
+				GBB@4K 448K
+				COREBOOT(CBFS)
+			}
+		}
+	}
+}

src/mainboard/amd/chausie/devicetree.cb

@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/amd/sabrina
+	register "common_config.espi_config" = "{
+		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN,
+		.io_mode = ESPI_IO_MODE_QUAD,
+		.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
+		.crc_check_enable = 1,
+		.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
+		.periph_ch_en = 1,
+		.vw_ch_en = 1,
+		.oob_ch_en = 1,
+		.flash_ch_en = 0,
+	}"
+
+	# I2C Pad Control RX Select Configuration
+	register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+	register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+	register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+	register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V"
+
+	register "s0ix_enable" = "true"
+
+	register "pspp_policy" = "DXIO_PSPP_BALANCED"
+
+	device domain 0 on
+		device ref iommu on end
+		device ref gpp_gfx_bridge_0 on end # MXM
+		device ref gpp_bridge_0 on end # NVMe
+		device ref gpp_bridge_1 on end
+		device ref gpp_bridge_2 on end # WWAN
+		device ref gpp_bridge_3 on end # LAN
+		device ref gpp_bridge_4 on end # WLAN
+		device ref gpp_bridge_5 on end
+		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
+			device ref gfx on end # Internal GPU (GFX)
+			device ref crypto on end # Crypto Coprocessor
+			device ref xhci_0 on # USB 3.1 (USB0)
+				chip drivers/usb/acpi
+					device ref xhci_0_root_hub on
+						chip drivers/usb/acpi
+							device ref usb3_port0 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb3_port1 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port0 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port1 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port2 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port3 on end
+						end
+					end
+				end
+			end
+			device ref xhci_1 on # USB 3.1 (USB1)
+				chip drivers/usb/acpi
+					device ref xhci_1_root_hub on
+						chip drivers/usb/acpi
+							device ref usb3_port4 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb3_port5 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port4 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port5 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port6 on end
+						end
+						chip drivers/usb/acpi
+							device ref usb2_port7 on end
+						end
+					end
+				end
+			end
+		end
+	end
+
+	device ref uart_0 on end # UART0
+
+end

src/mainboard/amd/chausie/dsdt.asl

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock (
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x00010001	/* OEM Revision */
+	)
+{
+	#include <acpi/dsdt_top.asl>
+
+	#include <soc.asl>
+}

src/mainboard/amd/chausie/early_gpio.c

@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "gpio.h"
+
+/* GPIO pins used by coreboot should be initialized in bootblock */
+
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
+	PAD_NF(GPIO_113, I2C2_SCL, PULL_NONE),
+	PAD_NF(GPIO_114, I2C2_SDA, PULL_NONE),
+	PAD_NF(GPIO_19, I2C3_SCL, PULL_NONE),
+	PAD_NF(GPIO_20, I2C3_SDA, PULL_NONE),
+};
+
+void mainboard_program_early_gpios(void)
+{
+	gpio_configure_pads(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset));
+}

src/mainboard/amd/chausie/gpio.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */
+
+#endif  /* MAINBOARD_GPIO_H */

src/mainboard/amd/chausie/mainboard.c

@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/amd_pci_util.h>
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <string.h>
+#include <types.h>
+
+/*
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system.  It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair.  These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ */
+static uint8_t fch_pic_routing[0x80];
+static uint8_t fch_apic_routing[0x80];
+
+_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing),
+	"PIC and APIC FCH interrupt tables must be the same size");
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ *  0: timer < soc/amd/common/acpi/lpc.asl
+ *  1: i8042 - Keyboard
+ *  2: cascade
+ *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ *  9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing {
+	uint8_t intr_index;
+	uint8_t pic_irq_num;
+	uint8_t apic_irq_num;
+} chausie_fch[] = {
+	{ PIRQ_A,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_B,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_C,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_D,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_E,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_F,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_G,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_H,	PIRQ_NC,	PIRQ_NC },
+
+	{ PIRQ_SCI,	ACPI_SCI_IRQ,	ACPI_SCI_IRQ },
+	{ PIRQ_SD,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SDIO,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_SATA,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_EMMC,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_GPIO,	7,		7 },
+	{ PIRQ_I2C2,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_I2C3,	PIRQ_NC,	PIRQ_NC },
+	{ PIRQ_UART0,	 4,		 4 },
+	{ PIRQ_UART1,	 3,		 3 },
+
+	/* The MISC registers are not interrupt numbers */
+	{ PIRQ_MISC,	0xfa,		0x00 },
+	{ PIRQ_MISC0,	0x91,		0x00 },
+	{ PIRQ_HPET_L,	0x00,		0x00 },
+	{ PIRQ_HPET_H,	0x00,		0x00 },
+};
+
+static void init_tables(void)
+{
+	const struct fch_irq_routing *entry;
+	int i;
+
+	memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing));
+	memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing));
+
+	for (i = 0; i < ARRAY_SIZE(chausie_fch); i++) {
+		entry = chausie_fch + i;
+		fch_pic_routing[entry->intr_index] = entry->pic_irq_num;
+		fch_apic_routing[entry->intr_index] = entry->apic_irq_num;
+	}
+}
+
+static void pirq_setup(void)
+{
+	intr_data_ptr = fch_apic_routing;
+	picr_data_ptr = fch_pic_routing;
+}
+
+static void mainboard_init(void *chip_info)
+{
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	init_tables();
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};

src/mainboard/amd/chausie/port_descriptors.c

@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <soc/platform_descriptors.h>
+#include <types.h>
+
+static const fsp_dxio_descriptor chausie_czn_dxio_descriptors[] = {
+	{ /* MXM */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 16,
+		.end_logical_lane = 23,
+		.device_number = 1,
+		.function_number = 1,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ0,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SSD */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 0,
+		.end_logical_lane = 1,
+		.device_number = 2,
+		.function_number = 1,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ5,
+		.gpio_group_id = GPIO_40,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* DT */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
+		.device_number = 2,
+		.function_number = 2,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ4_GFX,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* WWAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
+		.device_number = 2,
+		.function_number = 3,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ2,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* LAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 6,
+		.end_logical_lane = 6,
+		.device_number = 2,
+		.function_number = 4,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ1,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* WLAN */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 7,
+		.end_logical_lane = 7,
+		.device_number = 2,
+		.function_number = 5,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ6,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* TB */
+		.engine_type = PCIE_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 8,
+		.end_logical_lane = 11,
+		.device_number = 2,
+		.function_number = 6,
+		.turn_off_unused_lanes = true,
+		.clk_req = CLK_REQ3,
+		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
+	},
+	{ /* SATA */
+		.engine_type = SATA_ENGINE,
+		.port_present = true,
+		.start_logical_lane = 2,
+		.end_logical_lane = 3,
+		.channel_type = SATA_CHANNEL_LONG,
+	}
+};
+
+static const fsp_ddi_descriptor chausie_czn_ddi_descriptors[] = {
+	{ /* DDI0 - DP */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX1,
+		.hdp_index = DDI_HDP1
+	},
+	{ /* DDI1 - HDMI */
+		.connector_type = DDI_HDMI,
+		.aux_index = DDI_AUX2,
+		.hdp_index = DDI_HDP2
+	},
+	{ /* DDI2 */
+		.connector_type = DDI_UNUSED_TYPE,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI3 - DP (type C) */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX3,
+		.hdp_index = DDI_HDP3,
+	},
+	{ /* DDI4 - DP (type C) */
+		.connector_type = DDI_DP,
+		.aux_index = DDI_AUX4,
+		.hdp_index = DDI_HDP4,
+	}
+};
+
+void mainboard_get_dxio_ddi_descriptors(
+		const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
+		const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
+{
+	*dxio_descs = chausie_czn_dxio_descriptors;
+	*dxio_num = ARRAY_SIZE(chausie_czn_dxio_descriptors);
+	*ddi_descs = chausie_czn_ddi_descriptors;
+	*ddi_num = ARRAY_SIZE(chausie_czn_ddi_descriptors);
+}