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intel/e7505: Drop debug code 

Only (conditionally) used part was dump_pci_device()
and that was never particularly useful either.

Change-Id: Iaacfa511de1ce1e0bdbd2e8a74e41d336e505670
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2019-07-02 15:19:26 +03:00
parent 2020cbb6ed
commit a8dc3f58a9
4 changed files with 0 additions and 222 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/northbridge/intel/e7505/Makefile.inc
View File

@ -4,7 +4,6 @@ ramstage-y += northbridge.c
ramstage-y += memmap.c ramstage-y += memmap.c
romstage-y += raminit.c romstage-y += raminit.c
romstage-y += debug.c
romstage-y += memmap.c romstage-y += memmap.c
postcar-y += memmap.c postcar-y += memmap.c

186
src/northbridge/intel/e7505/debug.c
View File

@ -1,186 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <device/pci_def.h>
#include <console/console.h>
#include <stdlib.h>
#include <arch/io.h>
#include <device/pci_ops.h>
#include <spd.h>
#include "raminit.h"
#include "debug.h"
/*
* generic debug code, used by mainboard specific romstage.c
*
*/
void print_debug_pci_dev(unsigned dev)
{
printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
(dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
void print_pci_devices(void)
{
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
print_debug_pci_dev(dev);
printk(BIOS_DEBUG, "\n");
}
}
void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
for (i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
printk(BIOS_DEBUG, "\n");
}
void dump_pci_devices(void)
{
pci_devfn_t dev;
for (dev = PCI_DEV(0, 0, 0);
dev <= PCI_DEV(0xff, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
void dump_pci_devices_on_bus(unsigned busn)
{
pci_devfn_t dev;
for (dev = PCI_DEV(busn, 0, 0);
dev <= PCI_DEV(busn, 0x1f, 0x7);
dev += PCI_DEV(0,0,1)) {
uint32_t id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0xffff) ||
(((id >> 16) & 0xffff) == 0x0000)) {
continue;
}
dump_pci_device(dev);
}
}
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
printk(BIOS_DEBUG, "\n");
for (i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
}
}
void dump_smbus_registers(void)
{
unsigned device;
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
if (spd_read_byte(device, 0) < 0)
continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;
unsigned char byte;
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
}
void dump_io_resources(unsigned port)
{
int i;
printk(BIOS_DEBUG, "%04x:\n", port);
for (i = 0; i < 256; i++) {
uint8_t val;
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
printk(BIOS_DEBUG, "\n");
}
port++;
}
}

26
src/northbridge/intel/e7505/debug.h
View File

@ -1,26 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef E7505_DEBUG_H
#define E7505_DEBUG_H
void print_debug_pci_dev(unsigned dev);
void print_pci_devices(void);
void dump_pci_device(unsigned dev);
void dump_pci_devices(void);
void dump_pci_devices_on_bus(unsigned busn);
void dump_spd_registers(const struct mem_controller *ctrl);
void dump_smbus_registers(void);
void dump_io_resources(unsigned port);
#endif

9
src/northbridge/intel/e7505/raminit.c
View File

@ -43,7 +43,6 @@
#include "raminit.h" #include "raminit.h"
#include "e7505.h" #include "e7505.h"
#include "debug.h"
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
Definitions: Definitions:
@ -58,12 +57,10 @@ Definitions:
#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x) #define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x) #define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x) #define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(MCHDEV)
#else #else
#define RAM_DEBUG_MESSAGE(x) #define RAM_DEBUG_MESSAGE(x)
#define RAM_DEBUG_HEX32(x) #define RAM_DEBUG_HEX32(x)
#define RAM_DEBUG_HEX8(x) #define RAM_DEBUG_HEX8(x)
#define DUMPNORTH()
#endif #endif
#define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4)
@ -1768,9 +1765,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
*/ */
void e7505_mch_init(const struct mem_controller *memctrl) void e7505_mch_init(const struct mem_controller *memctrl)
{ {
RAM_DEBUG_MESSAGE("Northbridge prior to SDRAM init:\n");
DUMPNORTH();
timestamp_add_now(TS_BEFORE_INITRAM); timestamp_add_now(TS_BEFORE_INITRAM);
sdram_set_registers(memctrl); sdram_set_registers(memctrl);
@ -1783,9 +1777,6 @@ void e7505_mch_done(const struct mem_controller *memctrl)
sdram_post_ecc(memctrl); sdram_post_ecc(memctrl);
timestamp_add_now(TS_AFTER_INITRAM); timestamp_add_now(TS_AFTER_INITRAM);
RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n");
DUMPNORTH();
} }
int e7505_mch_is_ready(void) int e7505_mch_is_ready(void)