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soc/amd/common: Remove redundant ACPI S3 test 

Possible allowance to do wakeup is already evaluated
early in romstage, so these tests are redundant.

Change-Id: I7c7a9ecbfcb82790e477d906a00f9749103b4045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/27276
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2018-06-28 17:23:27 +03:00
parent 79cc577ba2
commit a8eb477c2e
3 changed files with 4 additions and 11 deletions
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9
src/soc/amd/common/block/pi/agesawrapper.c
View File

@ -422,9 +422,6 @@ AGESA_STATUS agesawrapper_amdinitresume(void)
};
size_t nv_size;
if (!acpi_s3_resume_allowed())
return AGESA_UNSUPPORTED;
AMD_RESUME_PARAMS *InitResumeParams = create_struct(&AmdParamStruct);
get_s3nv_info(&InitResumeParams->S3DataBlock.NvStorage, &nv_size);
@ -453,9 +450,6 @@ AGESA_STATUS agesawrapper_amds3laterestore(void)
};
size_t vol_size;
if (!acpi_s3_resume_allowed())
return AGESA_UNSUPPORTED;
amd_initcpuio();
AMD_S3LATE_PARAMS *S3LateParams = create_struct(&AmdParamStruct);
@ -488,9 +482,6 @@ AGESA_STATUS agesawrapper_amds3finalrestore(void)
};
size_t vol_size;
if (!acpi_s3_resume_allowed())
return AGESA_UNSUPPORTED;
AMD_S3FINAL_PARAMS *S3FinalParams = create_struct(&AmdParamStruct);
get_s3vol_info(&S3FinalParams->S3DataBlock.VolatileStorage, &vol_size);

2
src/soc/amd/stoneyridge/Kconfig
View File

@ -50,7 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_PI
select SOC_AMD_COMMON_BLOCK_PSP
select SOC_AMD_COMMON_BLOCK_CAR
select SOC_AMD_COMMON_BLOCK_S3 if HAVE_ACPI_RESUME
select SOC_AMD_COMMON_BLOCK_S3
select C_ENVIRONMENT_BOOTBLOCK
select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH

4
src/soc/amd/stoneyridge/chip.c
View File

@ -155,7 +155,9 @@ struct chip_operations soc_amd_stoneyridge_ops = {
static void earliest_ramstage(void *unused)
{
if (!romstage_handoff_is_resume()) {
int s3_resume = acpi_s3_resume_allowed() &&
romstage_handoff_is_resume();
if (!s3_resume) {
post_code(0x46);
if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");