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nb/intel/haswell: Fix DPR size handling 

DPR register's size field is given in whole MiB, so correct where it is
used to ensure the correct size multiple (KiB vs. MiB) is used with it.

Fixes: 5d7c3a4f0 ("nb/intel/haswell/northbridge.c: Correct DPR handling")

Change-Id: I3ca388907c61f1e47eab44ae8bc26e0f611fe1e3
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51104
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Wawrzynczak 2021-02-26 09:32:15 -07:00 committed by Patrick Georgi
parent d40a4c2bb4
commit a8f76904fb
1 changed files with 2 additions and 2 deletions
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4
src/northbridge/intel/haswell/northbridge.c
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@ -298,12 +298,12 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
/* 0xc0000 -> TSEG - DPR */
base_k = 0xc0000 >> 10;
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr.size >> 10;
size_k -= dpr.size * MiB / KiB;
ram_resource(dev, index++, base_k, size_k);
/* TSEG - DPR -> BGSM */
resource = new_resource(dev, index++);
resource->base = mc_values[TSEG_REG] - dpr.size;
resource->base = mc_values[TSEG_REG] - dpr.size * MiB;
resource->size = mc_values[BGSM_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;