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mb/google/brya/var/nivviks: Change bluetooth USB2 port from 8 to 10 

When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.

BUG=b:222595137
TEST=Bluetooth works on nivviks

Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
This commit is contained in:
Reka Norman 2022-03-04 13:18:50 +11:00 committed by Felix Held
parent 8565b94a53
commit a909c7f613
3 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb
View File

@ -25,7 +25,6 @@ chip soc/intel/alderlake
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A0
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1

1
src/mainboard/google/brya/variants/nereid/overridetree.cb
View File

@ -13,6 +13,7 @@ chip soc/intel/alderlake
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN
device domain 0 on device domain 0 on
device ref i2c1 on device ref i2c1 on

4
src/mainboard/google/brya/variants/nivviks/overridetree.cb
View File

@ -12,6 +12,8 @@ chip soc/intel/alderlake
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
device domain 0 on device domain 0 on
device ref ipu on device ref ipu on
chip drivers/intel/mipi_camera chip drivers/intel/mipi_camera
@ -300,7 +302,7 @@ chip soc/intel/alderlake
register "type" = "UPC_TYPE_INTERNAL" register "type" = "UPC_TYPE_INTERNAL"
register "reset_gpio" = register "reset_gpio" =
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
device ref usb2_port8 on end device ref usb2_port10 on end
end end
chip drivers/usb/acpi chip drivers/usb/acpi
register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "desc" = ""USB3 Type-A Port A0 (MLB)""