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docs: intel fsp: add memory retraining bug on SPS systems 

FSP2.0 forces MRC retraining on cold boot on Intel SPS systems.

Change-Id: I3ce812309b46bdb580557916a775043fda63667f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Michael Niewöhner 2019-11-18 19:51:57 +01:00 committed by Patrick Georgi
parent 6098da9ea8
commit a911216926
2 changed files with 7 additions and 1 deletions
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2
Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md
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@ -31,7 +31,7 @@ Look at the [flashing tutorial] and the board-specific section.
These issues apply to all boards. Have a look at the board-specific issues, too.
- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726)
- MRC caching does not work with cold boot
- MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0])
## ToDo

6
Documentation/soc/intel/fsp/index.md
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@ -34,6 +34,11 @@ those are fixed. If possible a workaround is described here as well.
* Workaround: none
* Issue on public tracker: [Issue 22]
* MRC forces memory re-training on cold boot on boards with Intel SPS
* Releases 3.7.1, 3.7.6
* Workaround: Flash Intel ME instead of SPS
* Issue on public tracker: [Issue 41]
### BraswellFsp
* Internal UART can't be disabled using PcdEnableHsuart*
* Release MR2
@ -66,4 +71,5 @@ those are fixed. If possible a workaround is described here as well.
[Issue 15]: https://github.com/IntelFsp/FSP/issues/15
[Issue 22]: https://github.com/IntelFsp/FSP/issues/22
[Issue 35]: https://github.com/IntelFsp/FSP/issues/35
[Issue 41]: https://github.com/IntelFsp/FSP/issues/41