diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 37f4d50b0b..ac42e0054a 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -157,6 +157,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	/* Configure VT-d */
 	tconfig->VtdDisable = 0;
 
+	/* Set HECI1 PCI BAR address */
+	m_cfg->Heci1BarAddress = HECI1_BASE_ADDRESS;
+
 	mainboard_memory_init_params(mupd);
 }