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mb/intel/adlrvp_m: Remove ASL code and enable dynamic SSDT creation for camera ACPI 

This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.

TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Varshit B Pandya 2021-06-21 22:20:09 +05:30 committed by Patrick Georgi
parent 048870ae2c
commit a932a471cc
2 changed files with 104 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/intel/adlrvp/Kconfig.name
View File

@ -15,7 +15,11 @@ config BOARD_INTEL_ADLRVP_M
bool "Alderlake-M RVP"
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
select DRIVERS_INTEL_MIPI_CAMERA
select SOC_INTEL_COMMON_BLOCK_IPU
config BOARD_INTEL_ADLRVP_M_EXT_EC
bool "Alderlake-M RVP with Chrome EC"
select INTEL_LPSS_UART_FOR_CONSOLE
select DRIVERS_INTEL_MIPI_CAMERA
select SOC_INTEL_COMMON_BLOCK_IPU

103
src/mainboard/intel/adlrvp/devicetree_m.cb
View File

@ -157,7 +157,21 @@ chip soc/intel/alderlake
device ref pcie5 on end
device ref igpu on end
device ref dtt on end
device ref ipu on end
device ref ipu on
chip drivers/intel/mipi_camera
register "acpi_uid" = "0x50000"
register "acpi_name" = ""IPU0""
register "device_type" = "INTEL_ACPI_CAMERA_CIO2"
register "cio2_num_ports" = "2"
register "cio2_lanes_used" = "{2,2}"
register "cio2_lane_endpoint[0]" = ""^I2C5.CAM1""
register "cio2_lane_endpoint[1]" = ""^I2C1.CAM0""
register "cio2_prt[0]" = "2"
register "cio2_prt[1]" = "1"
device generic 0 on end
end
end
device ref pcie4_0 on end
device ref pcie4_1 on end
device ref tbt_pcie_rp0 on end
@ -198,12 +212,95 @@ chip soc/intel/alderlake
end
end
device ref i2c0 on end
device ref i2c1 on end
device ref i2c1 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM0""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "ssdb.vcm_type" = "0x0C"
register "vcm_name" = ""VCM0""
register "num_freq_entries" = "1"
register "link_freq[0]" = "450000000"
register "remote_name" = ""IPU0""
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "0" #IMGCLKOUT_0
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_B23" #power_enable
register "gpio_panel.gpio[1].gpio_num" = "GPP_R5" #reset
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on end
end
chip drivers/intel/mipi_camera
register "acpi_uid" = "3"
register "acpi_name" = ""VCM0""
register "chip_name" = ""DW AF VCM""
register "device_type" = "INTEL_ACPI_CAMERA_VCM"
register "pr0" = ""\\_SB.PCI0.I2C1.CAM0.PRIC""
register "vcm_compat" = ""dongwoon,dw9714""
device i2c 0C on end
end
end
device ref i2c2 on end
device ref i2c3 on end
device ref heci1 on end
device ref sata on end
device ref i2c5 on end
device ref i2c5 on
chip drivers/intel/mipi_camera
register "acpi_hid" = ""OVTI5675""
register "acpi_uid" = "0"
register "acpi_name" = ""CAM1""
register "chip_name" = ""Ov 5675 Camera""
register "device_type" = "INTEL_ACPI_CAMERA_SENSOR"
register "ssdb.lanes_used" = "2"
register "num_freq_entries" = "1"
register "link_freq[0]" = "450000000"
register "remote_name" = ""IPU0""
register "has_power_resource" = "1"
#Controls
register "clk_panel.clks[0].clknum" = "1" #IMGCLKOUT_1
register "clk_panel.clks[0].freq" = "1" #19.2 Mhz
register "gpio_panel.gpio[0].gpio_num" = "GPP_E16" #power_enable
register "gpio_panel.gpio[1].gpio_num" = "GPP_E15" #reset
#_ON
register "on_seq.ops_cnt" = "4"
register "on_seq.ops[0]" = "SEQ_OPS_CLK_ENABLE(0, 0)"
register "on_seq.ops[1]" = "SEQ_OPS_GPIO_ENABLE(0, 2)"
register "on_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 1)"
register "on_seq.ops[3]" = "SEQ_OPS_GPIO_ENABLE(1, 1)"
#_OFF
register "off_seq.ops_cnt" = "3"
register "off_seq.ops[0]" = "SEQ_OPS_CLK_DISABLE(0, 0)"
register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(1, 0)"
register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(0, 0)"
device i2c 36 on end
end
end
device ref pcie_rp1 on end
device ref pcie_rp3 on end # W/A to FSP issue
device ref pcie_rp4 on end # W/A to FSP issue