mb/google/puff: update USB2 strength
Based on USB SI report to fine tune the strength for USB2 port0. BRANCH=none BUG=b:153590143 TEST=build and test USB2 port0 function works fine. Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
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@ -21,7 +21,14 @@ chip soc/intel/cannonlake
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}"
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}"
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# USB configuration
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# USB configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 2
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register "usb2_ports[1]" = "{
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register "usb2_ports[1]" = "{
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.enable = 1,
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.enable = 1,
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.ocpin = OC1,
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.ocpin = OC1,
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@ -21,7 +21,14 @@ chip soc/intel/cannonlake
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}"
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}"
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# USB configuration
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# USB configuration
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register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 2
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register "usb2_ports[1]" = "{
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register "usb2_ports[1]" = "{
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.enable = 1,
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.enable = 1,
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.ocpin = OC1,
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.ocpin = OC1,
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@ -24,7 +24,14 @@ chip soc/intel/cannonlake
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# NOTE: This only applies to Puff,
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# NOTE: This only applies to Puff,
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# usb2_ports[1] and usb2_ports[3] were swapped on
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# usb2_ports[1] and usb2_ports[3] were swapped on
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# reference schematics after Puff has been built.
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# reference schematics after Puff has been built.
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register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
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register "usb2_ports[0]" = "{
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.enable = 1,
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.ocpin = OC2,
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.tx_bias = USB2_BIAS_0MV,
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.tx_emp_enable = USB2_PRE_EMP_ON,
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.pre_emp_bias = USB2_BIAS_11P25MV,
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.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
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}" # Type-A Port 2
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
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register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
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register "usb2_ports[2]" = "{
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register "usb2_ports[2]" = "{
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.enable = 1,
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.enable = 1,
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