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mb/google/puff: update USB2 strength 

Based on USB SI report to fine tune the strength for USB2 port0.

BRANCH=none
BUG=b:153590143
TEST=build and test USB2 port0 function works fine.

Change-Id: I070c9e1c8153a680fb8f827889738a764d7ea9f4
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Tim Chen 2020-04-23 15:48:17 +08:00 committed by Edward O'Callaghan
parent 6c1a669b44
commit a932f6e507
3 changed files with 24 additions and 3 deletions
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9
src/mainboard/google/hatch/variants/duffy/overridetree.cb
View File

@ -21,7 +21,14 @@ chip soc/intel/cannonlake
}"
# USB configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC2,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 2
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC1,

9
src/mainboard/google/hatch/variants/kaisa/overridetree.cb
View File

@ -21,7 +21,14 @@ chip soc/intel/cannonlake
}"
# USB configuration
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC2,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 2
register "usb2_ports[1]" = "{
.enable = 1,
.ocpin = OC1,

9
src/mainboard/google/hatch/variants/puff/overridetree.cb
View File

@ -24,7 +24,14 @@ chip soc/intel/cannonlake
# NOTE: This only applies to Puff,
# usb2_ports[1] and usb2_ports[3] were swapped on
# reference schematics after Puff has been built.
register "usb2_ports[0]" = "USB2_PORT_MID(OC2)" # Type-A Port 2
register "usb2_ports[0]" = "{
.enable = 1,
.ocpin = OC2,
.tx_bias = USB2_BIAS_0MV,
.tx_emp_enable = USB2_PRE_EMP_ON,
.pre_emp_bias = USB2_BIAS_11P25MV,
.pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
}" # Type-A Port 2
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
register "usb2_ports[2]" = "{
.enable = 1,