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src: Replace common MSR addresses with macros 

Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This commit is contained in:
Elyes HAOUAS 2018-10-24 15:55:53 +02:00 committed by Patrick Georgi
parent f33e835a06
commit a9473ecbb1
8 changed files with 12 additions and 24 deletions
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2
src/cpu/amd/microcode/microcode.c
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@ -127,7 +127,7 @@ static void apply_microcode_patch(const struct microcode *m)
UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id); UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
/* read the patch_id again */ /* read the patch_id again */
msr = rdmsr(0x8b); msr = rdmsr(IA32_BIOS_SIGN_ID);
new_patch_id = msr.lo; new_patch_id = msr.lo;
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id, UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,

3
src/cpu/x86/lapic/boot_cpu.c
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@ -13,13 +13,14 @@
#include <smp/node.h> #include <smp/node.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/lapic_def.h>
#if IS_ENABLED(CONFIG_SMP) #if IS_ENABLED(CONFIG_SMP)
int boot_cpu(void) int boot_cpu(void)
{ {
int bsp; int bsp;
msr_t msr; msr_t msr;
msr = rdmsr(0x1b); msr = rdmsr(LAPIC_BASE_MSR);
bsp = !!(msr.lo & (1 << 8)); bsp = !!(msr.lo & (1 << 8));
return bsp; return bsp;
} }

6
src/cpu/x86/smm/smmhandler.S
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@ -21,7 +21,7 @@
* to 64k if we can though. * to 64k if we can though.
*/ */
#define LAPIC_BASE_MSR 0x1b #include <cpu/x86/lapic_def.h>
/* /*
* +--------------------------------+ 0xaffff * +--------------------------------+ 0xaffff
@ -49,8 +49,6 @@
* *
*/ */
#define LAPIC_ID 0xfee00020
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
* at which smm_handler_start lives. At the moment the handler * at which smm_handler_start lives. At the moment the handler
* lives right at 0xa0000, so the offset is 0. * lives right at 0xa0000, so the offset is 0.
@ -134,7 +132,7 @@ untampered_lapic:
movw %ax, %gs movw %ax, %gs
/* Get this CPU's LAPIC ID */ /* Get this CPU's LAPIC ID */
movl $LAPIC_ID, %esi movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi
movl (%esi), %ecx movl (%esi), %ecx
shr $24, %ecx shr $24, %ecx

1
src/include/cpu/x86/msr.h
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@ -14,6 +14,7 @@
#define EFER_SCE (1 << 0) #define EFER_SCE (1 << 0)
/* Page attribute type MSR */ /* Page attribute type MSR */
#define TSC_MSR 0x10
#define IA32_PLATFORM_ID 0x17 #define IA32_PLATFORM_ID 0x17
#define IA32_FEATURE_CONTROL 0x3a #define IA32_FEATURE_CONTROL 0x3a
#define FEATURE_CONTROL_LOCK_BIT (1 << 0) #define FEATURE_CONTROL_LOCK_BIT (1 << 0)

9
src/northbridge/amd/amdht/AsPsDefs.h
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@ -18,9 +18,6 @@
#ifndef ASPSDEFS_H #ifndef ASPSDEFS_H
#define ASPSDEFS_H #define ASPSDEFS_H
#define APIC_BAR 0x1b /* APIC_BAR register */
#define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */
/* P-state register offset */ /* P-state register offset */
#define PS_REG0 0 /* offset for P0 */ #define PS_REG0 0 /* offset for P0 */
#define PS_REG1 1 /* offset for P1 */ #define PS_REG1 1 /* offset for P1 */
@ -237,7 +234,6 @@
#define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */ #define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */
#define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */ #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */
#define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */ #define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */
/* sFidVidInit.outFlags defines */ /* sFidVidInit.outFlags defines */
@ -259,7 +255,6 @@
#define VID_1_100V 0x12 /* 1.100V */ #define VID_1_100V 0x12 /* 1.100V */
#define VID_1_175V 0x1E /* 1.175V */ #define VID_1_175V 0x1E /* 1.175V */
/* Nb Fid Code */ /* Nb Fid Code */
#define NB_FID_800M 0x00 /* 800MHz */ #define NB_FID_800M 0x00 /* 800MHz */
@ -268,13 +263,9 @@
#define NB_DID_1 1 #define NB_DID_1 1
/* GH Logical ID */ /* GH Logical ID */
#define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */ #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */
#define TSC_MSR 0x10
#define TSC_FREQ_SEL_SHIFT 24 #define TSC_FREQ_SEL_SHIFT 24
#define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ #define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */

9
src/northbridge/amd/amdht/h3finit.c
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@ -29,6 +29,7 @@
#include <device/pci.h> #include <device/pci.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/x86/lapic_def.h>
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
@ -42,10 +43,6 @@
*---------------------------------------------------------------------------- *----------------------------------------------------------------------------
*/ */
/* APIC defines from amdgesa.inc, which can't be included in to c code. */
#define APIC_Base_BSP 8
#define APIC_Base 0x1b
#define NVRAM_LIMIT_HT_SPEED_200 0x12 #define NVRAM_LIMIT_HT_SPEED_200 0x12
#define NVRAM_LIMIT_HT_SPEED_300 0x11 #define NVRAM_LIMIT_HT_SPEED_300 0x11
#define NVRAM_LIMIT_HT_SPEED_400 0x10 #define NVRAM_LIMIT_HT_SPEED_400 0x10
@ -1831,9 +1828,9 @@ static BOOL isSanityCheckOk(void)
{ {
uint64 qValue; uint64 qValue;
AmdMSRRead(APIC_Base, &qValue); AmdMSRRead(LAPIC_BASE_MSR, &qValue);
return ((qValue.lo & ((u32)1 << APIC_Base_BSP)) != 0); return ((qValue.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) != 0);
} }
/*************************************************************************** /***************************************************************************

4
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
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@ -2364,10 +2364,10 @@ void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanoseconds) {
uint64_t start_timestamp; uint64_t start_timestamp;
uint64_t current_timestamp; uint64_t current_timestamp;
tsc_msr = rdmsr(0x00000010); tsc_msr = rdmsr(TSC_MSR);
start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
do { do {
tsc_msr = rdmsr(0x00000010); tsc_msr = rdmsr(TSC_MSR);
current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
} while ((current_timestamp - start_timestamp) < cycle_count); } while ((current_timestamp - start_timestamp) < cycle_count);
} }

2
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
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@ -2427,7 +2427,7 @@ void mct_Wait(u32 cycles)
cycles <<= 3; /* x8 (number of 1.25ns ticks) */ cycles <<= 3; /* x8 (number of 1.25ns ticks) */
msr = 0x10; /* TSC */ msr = TSC_MSR; /* TSC */
_RDMSR(msr, &lo, &hi); _RDMSR(msr, &lo, &hi);
saved = lo; saved = lo;
do { do {