link/graphics: New state machine
This is a new state machine. It is more programmatic, in the case of auxio, and has much more symbolic naming, and very few "magic" numbers, except in the case of undocumented settings. As before, the 'pre-computed' IO ops are encoded in the iodefs table. A function, run, is passed and index into the table and runs the ops. A new operator, I, has been added. When the I operator is hit, run() returns the index of the next operator in the table. The i915lightup function runs the table. All the AUX channel ops have been removed from the table, however, and are now called as functions, using the previously committed auxio function. The iodefs table has been grouped into blocks of ops, which end in an I operator. As the lightup function progresses through startup, and the run() returns, the lightup function performs aux channel operations. This code is symbolic enough, I hope, that it will make haswell graphics bringup simpler. i915io.c, and the core of the code in i915lightup.c, were programatically generated, starting with IO logs from the DRM startup code in the kernel. It is possible to apply the tools that do this generation to newer IO logs from the kernel. Change-Id: I8a8e121dc0d9674f0c6a866343b28e179a1e3d8a Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2836 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich
Stefan Reinauer
parent
ec2d914e19
commit
a95a13bd47
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@ -0,0 +1,239 @@
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/*
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* Copyright 2013 Google Inc.
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* Copyright © 2008 Keith Packard
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*
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* Permission to use, copy, modify, distribute, and sell this software and its
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* documentation for any purpose is hereby granted without fee, provided that
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* the above copyright notice appear in all copies and that both that copyright
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* notice and this permission notice appear in supporting documentation, and
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* that the name of the copyright holders not be used in advertising or
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* publicity pertaining to distribution of the software without specific,
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* written prior permission. The copyright holders make no representations
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* about the suitability of this software for any purpose. It is provided "as
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* is" without express or implied warranty.
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*
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* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
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* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
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* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
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* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
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* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
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* OF THIS SOFTWARE.
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*/
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#ifndef _DRM_DP_HELPER_H_
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#define _DRM_DP_HELPER_H_
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/* From the VESA DisplayPort spec */
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#define AUX_NATIVE_WRITE 0x8
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#define AUX_NATIVE_READ 0x9
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#define AUX_I2C_WRITE 0x0
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#define AUX_I2C_READ 0x1
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#define AUX_I2C_STATUS 0x2
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#define AUX_I2C_MOT 0x4
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#define AUX_NATIVE_REPLY_ACK (0x0 << 4)
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#define AUX_NATIVE_REPLY_NACK (0x1 << 4)
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#define AUX_NATIVE_REPLY_DEFER (0x2 << 4)
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#define AUX_NATIVE_REPLY_MASK (0x3 << 4)
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#define AUX_I2C_REPLY_ACK (0x0 << 6)
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#define AUX_I2C_REPLY_NACK (0x1 << 6)
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#define AUX_I2C_REPLY_DEFER (0x2 << 6)
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#define AUX_I2C_REPLY_MASK (0x3 << 6)
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/* AUX CH addresses */
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/* DPCD */
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#define DP_DPCD_REV 0x000
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#define DP_MAX_LINK_RATE 0x001
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#define DP_MAX_LANE_COUNT 0x002
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# define DP_MAX_LANE_COUNT_MASK 0x1f
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# define DP_TPS3_SUPPORTED (1 << 6)
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# define DP_ENHANCED_FRAME_CAP (1 << 7)
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#define DP_MAX_DOWNSPREAD 0x003
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# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
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#define DP_NORP 0x004
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#define DP_DOWNSTREAMPORT_PRESENT 0x005
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# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
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# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
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/* 00b = DisplayPort */
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/* 01b = Analog */
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/* 10b = TMDS or HDMI */
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/* 11b = Other */
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# define DP_FORMAT_CONVERSION (1 << 3)
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#define DP_MAIN_LINK_CHANNEL_CODING 0x006
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#define DP_EDP_CONFIGURATION_CAP 0x00d
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#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
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#define DP_PSR_SUPPORT 0x070
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# define DP_PSR_IS_SUPPORTED 1
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#define DP_PSR_CAPS 0x071
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# define DP_PSR_NO_TRAIN_ON_EXIT 1
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# define DP_PSR_SETUP_TIME_330 (0 << 1)
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# define DP_PSR_SETUP_TIME_275 (1 << 1)
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# define DP_PSR_SETUP_TIME_220 (2 << 1)
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# define DP_PSR_SETUP_TIME_165 (3 << 1)
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# define DP_PSR_SETUP_TIME_110 (4 << 1)
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# define DP_PSR_SETUP_TIME_55 (5 << 1)
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# define DP_PSR_SETUP_TIME_0 (6 << 1)
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# define DP_PSR_SETUP_TIME_MASK (7 << 1)
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# define DP_PSR_SETUP_TIME_SHIFT 1
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/* link configuration */
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#define DP_LINK_BW_SET 0x100
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# define DP_LINK_BW_1_62 0x06
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# define DP_LINK_BW_2_7 0x0a
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# define DP_LINK_BW_5_4 0x14
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#define DP_LANE_COUNT_SET 0x101
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# define DP_LANE_COUNT_MASK 0x0f
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# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
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#define DP_TRAINING_PATTERN_SET 0x102
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# define DP_TRAINING_PATTERN_DISABLE 0
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# define DP_TRAINING_PATTERN_1 1
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# define DP_TRAINING_PATTERN_2 2
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# define DP_TRAINING_PATTERN_3 3
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# define DP_TRAINING_PATTERN_MASK 0x3
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# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
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# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2)
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# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2)
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# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2)
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# define DP_LINK_QUAL_PATTERN_MASK (3 << 2)
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# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4)
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# define DP_LINK_SCRAMBLING_DISABLE (1 << 5)
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# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6)
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# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6)
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# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6)
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# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6)
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#define DP_TRAINING_LANE0_SET 0x103
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#define DP_TRAINING_LANE1_SET 0x104
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#define DP_TRAINING_LANE2_SET 0x105
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#define DP_TRAINING_LANE3_SET 0x106
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# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3
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# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0
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# define DP_TRAIN_MAX_SWING_REACHED (1 << 2)
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# define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0)
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# define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0)
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# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3)
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# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3
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# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5)
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#define DP_DOWNSPREAD_CTRL 0x107
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# define DP_SPREAD_AMP_0_5 (1 << 4)
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#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
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# define DP_SET_ANSI_8B10B (1 << 0)
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#define DP_PSR_EN_CFG 0x170
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# define DP_PSR_ENABLE (1 << 0)
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# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
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# define DP_PSR_CRC_VERIFICATION (1 << 2)
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# define DP_PSR_FRAME_CAPTURE (1 << 3)
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#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
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# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
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# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
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# define DP_CP_IRQ (1 << 2)
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# define DP_SINK_SPECIFIC_IRQ (1 << 6)
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#define DP_EDP_CONFIGURATION_SET 0x10a
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#define DP_LANE0_1_STATUS 0x202
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#define DP_LANE2_3_STATUS 0x203
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# define DP_LANE_CR_DONE (1 << 0)
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# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
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# define DP_LANE_SYMBOL_LOCKED (1 << 2)
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#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
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DP_LANE_CHANNEL_EQ_DONE | \
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DP_LANE_SYMBOL_LOCKED)
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#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
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#define DP_INTERLANE_ALIGN_DONE (1 << 0)
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#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
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#define DP_LINK_STATUS_UPDATED (1 << 7)
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#define DP_SINK_STATUS 0x205
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#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
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#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
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#define DP_ADJUST_REQUEST_LANE0_1 0x206
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#define DP_ADJUST_REQUEST_LANE2_3 0x207
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
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# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
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# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
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# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
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# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
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#define DP_TEST_REQUEST 0x218
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# define DP_TEST_LINK_TRAINING (1 << 0)
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# define DP_TEST_LINK_PATTERN (1 << 1)
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# define DP_TEST_LINK_EDID_READ (1 << 2)
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# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */
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#define DP_TEST_LINK_RATE 0x219
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# define DP_LINK_RATE_162 (0x6)
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# define DP_LINK_RATE_27 (0xa)
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#define DP_TEST_LANE_COUNT 0x220
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#define DP_TEST_PATTERN 0x221
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#define DP_TEST_RESPONSE 0x260
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# define DP_TEST_ACK (1 << 0)
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# define DP_TEST_NAK (1 << 1)
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# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2)
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#define DP_SET_POWER 0x600
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# define DP_SET_POWER_D0 0x1
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# define DP_SET_POWER_D3 0x2
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#define DP_PSR_ERROR_STATUS 0x2006
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# define DP_PSR_LINK_CRC_ERROR (1 << 0)
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# define DP_PSR_RFB_STORAGE_ERROR (1 << 1)
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#define DP_PSR_ESI 0x2007
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# define DP_PSR_CAPS_CHANGE (1 << 0)
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#define DP_PSR_STATUS 0x2008
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# define DP_PSR_SINK_INACTIVE 0
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# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1
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# define DP_PSR_SINK_ACTIVE_RFB 2
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# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3
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# define DP_PSR_SINK_ACTIVE_RESYNC 4
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# define DP_PSR_SINK_INTERNAL_ERROR 7
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# define DP_PSR_SINK_STATE_MASK 0x07
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#define MODE_I2C_START 1
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#define MODE_I2C_WRITE 2
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#define MODE_I2C_READ 4
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#define MODE_I2C_STOP 8
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#endif /* _DRM_DP_HELPER_H_ */
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@ -19,6 +19,7 @@
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#include <types.h>
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#include <string.h>
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#include <stdlib.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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@ -62,18 +63,29 @@ extern int oprom_is_loaded;
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#define READ32(addr) io_i915_READ32(addr)
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#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
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static char *regname(unsigned long addr)
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{
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static char name[16];
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sprintf(name, "0x%lx", addr);
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return name;
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}
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unsigned long io_i915_READ32(unsigned long addr)
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{
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unsigned long val;
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outl(addr, addrport);
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val = inl(dataport);
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return val;
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unsigned long val;
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outl(addr, addrport);
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val = inl(dataport);
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
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return val;
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}
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void io_i915_WRITE32(unsigned long val, unsigned long addr)
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{
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outl(addr, addrport);
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outl(val, dataport);
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if (verbose & vio)
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printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
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outl(addr, addrport);
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outl(val, dataport);
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}
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@ -101,13 +113,6 @@ setgtt(int start, int end, unsigned long base, int inc)
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}
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}
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static char *regname(unsigned long addr)
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{
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static char name[16];
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sprintf(name, "0x%lx", addr);
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return name;
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}
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static unsigned long tickspermicrosecond = 1795;
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static unsigned long long globalstart;
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@ -125,6 +130,7 @@ static unsigned long globalmicroseconds(void)
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}
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extern struct iodef iodefs[];
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extern int niodefs;
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static int i915_init_done = 0;
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@ -134,11 +140,7 @@ static void palette(void)
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int i;
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unsigned long color = 0;
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for (i = 0; i < 256; i++, color += 0x010101){
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if (verbose & vio)printk(BIOS_SPEW,
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"_LGC_PALETTE_A+%08x: outl %08lx\n",
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i<<2, color);
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for(i = 0; i < 256; i++, color += 0x010101){
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io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
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}
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}
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@ -169,31 +171,15 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
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}
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int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
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unsigned int gfx);
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static unsigned long times[4096];
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int i915lightup(unsigned int pphysbase,
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unsigned int piobase,
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unsigned int pmmio,
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unsigned int pgfx)
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static int run(int index)
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{
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int i, prev = 0;
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struct iodef *id, *lastidread = 0;
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unsigned long u, t;
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static unsigned long times[4096];
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mmio = (void *)pmmio;
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addrport = piobase;
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dataport = addrport + 4;
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physbase = pphysbase;
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graphics = pgfx;
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printk(BIOS_SPEW,
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"i915lightup: graphics %p mmio %p"
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"addrport %04x physbase %08x\n",
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(void *)graphics, mmio, addrport, physbase);
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globalstart = rdtscll();
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/* state machine! */
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for (i = 0, id = iodefs; id->op; i++, id++){
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for(i = index, id = &iodefs[i]; id->op; i++, id++){
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switch(id->op){
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case M:
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if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
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@ -204,8 +190,8 @@ int i915lightup(unsigned int pphysbase,
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break;
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case R:
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u = READ32(id->addr);
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if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx, expect %08lx\n",
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regname(id->addr), u, id->data);
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if (verbose & vio)
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printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
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/* we're looking for something. */
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if (lastidread->addr == id->addr){
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/* they're going to be polling.
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@ -222,14 +208,16 @@ int i915lightup(unsigned int pphysbase,
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lastidread = id;
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break;
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case W:
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if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(id->addr),
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id->data);
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WRITE32(id->data, id->addr);
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if (id->addr == PCH_PP_CONTROL){
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if (verbose & vio)
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printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
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switch(id->data & 0xf){
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case 8: break;
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case 7: break;
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default: udelay(100000);
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if (verbose & vio)
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printk(BIOS_SPEW, "U %d\n", 100000);
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}
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}
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break;
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@ -240,8 +228,11 @@ int i915lightup(unsigned int pphysbase,
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} else {
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verbose = prev;
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}
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printk(BIOS_SPEW, "Change verbosity to %d\n", verbose);
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break;
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case I:
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printk(BIOS_SPEW, "run: return %d\n", i+1);
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return i+1;
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break;
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default:
|
||||
printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
|
||||
|
|
@ -249,27 +240,125 @@ int i915lightup(unsigned int pphysbase,
|
|||
}
|
||||
if (id->udelay)
|
||||
udelay(id->udelay);
|
||||
times[i] = globalmicroseconds();
|
||||
}
|
||||
/* optional, we don't even want to take timestamp overhead
|
||||
* if we can avoid it. */
|
||||
if (0)
|
||||
for (i = 0, id = iodefs; id->op; i++, id++){
|
||||
switch(id->op){
|
||||
case R:
|
||||
printk(BIOS_SPEW, "%ld: R %08lx\n", times[i], id->addr);
|
||||
break;
|
||||
case W:
|
||||
printk(BIOS_SPEW, "%ld: W %08lx %08lx\n", times[i],
|
||||
id->addr, id->data);
|
||||
break;
|
||||
}
|
||||
if (i < ARRAY_SIZE(times))
|
||||
times[i] = globalmicroseconds();
|
||||
}
|
||||
printk(BIOS_SPEW, "run: return %d\n", i);
|
||||
return i+1;
|
||||
}
|
||||
|
||||
setgtt(0, 4520, physbase, 4096);
|
||||
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
|
||||
unsigned int gfx);
|
||||
|
||||
int i915lightup(unsigned int pphysbase, unsigned int piobase,
|
||||
unsigned int pmmio, unsigned int pgfx)
|
||||
{
|
||||
int index;
|
||||
u32 auxin[16], auxout[16];
|
||||
mmio = (void *)pmmio;
|
||||
addrport = piobase;
|
||||
dataport = addrport + 4;
|
||||
physbase = pphysbase;
|
||||
graphics = pgfx;
|
||||
printk(BIOS_SPEW,
|
||||
"i915lightup: graphics %p mmio %p"
|
||||
"addrport %04x physbase %08x\n",
|
||||
(void *)graphics, mmio, addrport, physbase);
|
||||
globalstart = rdtscll();
|
||||
|
||||
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
|
||||
index = run(0);
|
||||
printk(BIOS_SPEW, "Run returns %d\n", index);
|
||||
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14);
|
||||
auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
|
||||
index = run(index);
|
||||
printk(BIOS_SPEW, "Run returns %d\n", index);
|
||||
auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
|
||||
index = run(index);
|
||||
printk(BIOS_SPEW, "Run returns %d\n", index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0;
|
||||
auxout[1] = 0x01000000;
|
||||
/* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE */
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8;
|
||||
auxout[1] = 0x0a840000;
|
||||
/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
|
||||
auxout[2] = 0x00000000;
|
||||
auxout[3] = 0x01000000;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
|
||||
auxout[1] = 0x21000000;
|
||||
/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
|
||||
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
|
||||
auxout[1] = 0x00000000;
|
||||
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
|
||||
auxout[1] = 0x22000000;
|
||||
/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
|
||||
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
|
||||
auxout[1] = 0x00000000;
|
||||
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
|
||||
index = run(index);
|
||||
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
|
||||
auxout[1] = 0x00000000;
|
||||
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
|
||||
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
|
||||
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
|
||||
index = run(index);
|
||||
|
||||
if (index != niodefs)
|
||||
printk(BIOS_ERR, "Left over IO work in i915_lightup"
|
||||
" -- this is likely a table error. "
|
||||
"Only %d of %d were done.\n", index, niodefs);
|
||||
printk(BIOS_SPEW, "DONE startup\n");
|
||||
verbose = 0;
|
||||
/* GTT is the Global Translation Table for the graphics pipeline.
|
||||
* It is used to translate graphics addresses to physical
|
||||
* memory addresses. As in the CPU, GTTs map 4K pages.
|
||||
* There are 32 bits per pixel, or 4 bytes,
|
||||
* which means 1024 pixels per page.
|
||||
* There are 4250 GTTs on Link:
|
||||
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
|
||||
* The setgtt function adds a further bit of flexibility:
|
||||
* it allows you to set a range (the first two parameters) to point
|
||||
* to a physical address (third parameter);the physical address is
|
||||
* incremented by a count (fourth parameter) for each GTT in the
|
||||
* range.
|
||||
* Why do it this way? For ultrafast startup,
|
||||
* we can point all the GTT entries to point to one page,
|
||||
* and set that page to 0s:
|
||||
* memset(physbase, 0, 4096);
|
||||
* setgtt(0, 4250, physbase, 0);
|
||||
* this takes about 2 ms, and is a win because zeroing
|
||||
* the page takes a up to 200 ms. We will be exploiting this
|
||||
* trick in a later rev of this code.
|
||||
* This call sets the GTT to point to a linear range of pages
|
||||
* starting at physbase.
|
||||
*/
|
||||
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
|
||||
printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n",
|
||||
(void *)graphics, 4520*4096);
|
||||
memset((void *)graphics, 0, 4520*4096);
|
||||
(void *)graphics, FRAME_BUFFER_BYTES);
|
||||
memset((void *)graphics, 0, FRAME_BUFFER_BYTES);
|
||||
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds());
|
||||
i915_init_done = 1;
|
||||
oprom_is_loaded = 1;
|
||||
|
|
|
|||
|
|
@ -16,485 +16,342 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "i915io.h"
|
||||
|
||||
struct iodef iodefs[] = {
|
||||
{V,0,},
|
||||
//{V, 7, },
|
||||
{W, 1, "", PCH_GMBUS0, 0x00000000, },
|
||||
{R, 1, "", PP_ON_DELAYS, 0x00000000, },
|
||||
{R, 1, "", PP_OFF_DELAYS, 0x00000000, },
|
||||
{W, 1, "", PP_ON_DELAYS, 0x019007d0, },
|
||||
{W, 1, "", PP_OFF_DELAYS, 0x015e07d0, },
|
||||
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH"},
|
||||
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables"},
|
||||
{R, 50, "", 0x130040, 0x00000001, 10},
|
||||
{W, 1, "", 0xa188, 0x00010001, },
|
||||
{R, 1, "", 0xa188, 0x00010001, },
|
||||
{R, 1, "", 0x130040, 0x00000001, },
|
||||
{R, 1, "", 0x13805c, 0x40000000, },
|
||||
{R, 1, "", 0xa180, 0x84100020, },
|
||||
{W, 1, "", 0xa188, 0x00010000, },
|
||||
{R, 1, "", 0x120000, 0x00000000, },
|
||||
{M, 1, "[drm:intel_init_display], Using MT version of forcewake"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:intel_modeset_init], 3 display pipes available."},
|
||||
{R, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{R, 1, "", 0x72008, 0x00000000, },
|
||||
{W, 1, "", 0x72008, 0x00000000, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{R, 1, "", 0x72008, 0x00000000, },
|
||||
{W, 1, "", 0x72008, 0x00000000, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, },
|
||||
{R, 1, "", 0x72008, 0x00000000, },
|
||||
{W, 1, "", 0x72008, 0x00000000, 300},
|
||||
{W, 1, "", CPU_VGACNTRL, 0x80000000, },
|
||||
{R, 1, "", CPU_VGACNTRL, 0x80000000, },
|
||||
{R, 1, "", 0x64000, 0x0000001c, },
|
||||
{R, 1, "", PCH_PP_ON_DELAYS, 0x47d007d0, },
|
||||
{R, 1, "", PCH_PP_OFF_DELAYS, 0x01f407d0, },
|
||||
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, },
|
||||
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500"
|
||||
"t11_t12 6000"},
|
||||
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0"},
|
||||
{M, 1, "[drm:intel_dp_init], panel power up delay 200,"
|
||||
"power down delay 50, power cycle delay 600"},
|
||||
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200"},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000"},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, },
|
||||
{W, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008"},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running"},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x014300c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x9000000e, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x814500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x810500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x410500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x530500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00110a84, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA2, 0x41000001, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA3, 0xc0020000, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA4, 0x001f0000, },
|
||||
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A"},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x010500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x40000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x810500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd23500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
|
||||
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, },
|
||||
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302"},
|
||||
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f"},
|
||||
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110"},
|
||||
{M, 1,
|
||||
"[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 has_pch_edp 0"
|
||||
"has_cpu_edp 1 has_ck505 0"},
|
||||
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel"},
|
||||
{W, 1, "", PCH_DREF_CONTROL, 0x00001402, },
|
||||
{R, 1, "", PCH_DREF_CONTROL, 0x00001402, 200},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP"},
|
||||
{W, 1, "", PCH_DREF_CONTROL, 0x00005402, },
|
||||
{R, 1, "", PCH_DREF_CONTROL, 0x00005402, 200},
|
||||
{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
|
||||
{W, 1, "", WM3_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM2_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM1_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", 0x9404, 0x00002000, },
|
||||
{W, 1, "", ILK_DSPCLK_GATE, 0x10000000, },
|
||||
{W, 1, "", IVB_CHICKEN3, 0x00000024, },
|
||||
{W, 1, "", 0x7010, 0x04000400, },
|
||||
{W, 1, "", 0xb01c, 0x3c4fff8c, },
|
||||
{W, 1, "", 0xb030, 0x20000000, },
|
||||
{R, 1, "", 0x9030, 0x00000000, },
|
||||
{W, 1, "", 0x9030, 0x00000800, },
|
||||
{R, 1, "", _DSPACNTR, 0x00000000, },
|
||||
{W, 1, "", _DSPACNTR, 0x00004000, },
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, },
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, },
|
||||
{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
|
||||
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
|
||||
{R, 1, "", _DSPBCNTR, 0x00000000, },
|
||||
{W, 1, "", _DSPBCNTR, 0x00004000, },
|
||||
{R, 1, "", _DSPBADDR, 0x00000000, },
|
||||
{W, 1, "", _DSPBADDR, 0x00000000, },
|
||||
{R, 1, "", _DSPBSURF, 0x00000000, },
|
||||
{W, 1, "", _DSPBSURF, 0x00000000, },
|
||||
{R, 1, "", _DVSACNTR, 0x00000000, },
|
||||
{W, 1, "", _DVSACNTR, 0x00004000, },
|
||||
{R, 1, "", _DVSALINOFF, 0x00000000, },
|
||||
{W, 1, "", _DVSALINOFF, 0x00000000, },
|
||||
{R, 1, "", _DVSASURF, 0x00000000, },
|
||||
{W, 1, "", _DVSASURF, 0x00000000, },
|
||||
{W, 1, "", SOUTH_DSPCLK_GATE_D, 0x20000000, },
|
||||
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, },
|
||||
{W, 1, "", SOUTH_CHICKEN2, 0x00000001, },
|
||||
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, },
|
||||
{W, 1, "", _TRANSB_CHICKEN2, 0x80000000, },
|
||||
/* to here, it works ok with v0 */
|
||||
//{V, 7,},
|
||||
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found"},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"
|
||||
"probed modes :"},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],"
|
||||
"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
|
||||
"0x48 0xa"},
|
||||
{M, 1, "[drm:drm_setup_crtcs], "},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
|
||||
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config"},
|
||||
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3"},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]"},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
|
||||
//{V, 7,},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0"},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes"},
|
||||
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],"
|
||||
"[ENCODER:7:TMDS-7]"},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
|
||||
"clock 270000"},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80060000, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x01000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{R, 1, "", 0x64000, 0x0000001c, },
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
|
||||
#if 0
|
||||
/* I hope we never try to use this. It is left here as a documentation thing. */
|
||||
/* SCALING HACK */
|
||||
/* these were determined by reading registers.
|
||||
* They should stretch the display.
|
||||
* They don't.
|
||||
* From u-boot? After vbios?
|
||||
*/
|
||||
{V, 7, },
|
||||
{M, 1, "Turning on panel fitter (must be done before power cycle)"},
|
||||
{W, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, },
|
||||
/* status: can't ever set vscale.
|
||||
* Which may be why we get no display at all if we try. */
|
||||
{W, 1, "stretch", _PFA_VSCALE, /*0x00004000*/0xffffffff, },
|
||||
{W, 1, "stretch", _PFA_HSCALE, /*0x00004000*/0xffffffff, },
|
||||
{W, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, },
|
||||
//{W, 1, "2560x1700", _PFA_WIN_SZ, 0x05000352, },
|
||||
{W, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, },
|
||||
{R, 1, "Vstretch", _PFA_VSCALE, 0x00004000, },
|
||||
{R, 1, "Hstretch", _PFA_HSCALE, 0x00004000, },
|
||||
{R, 1, "2560x1700", _PFA_WIN_SZ, 0x0a0006a4, },
|
||||
{R, 1, "@[0,0]", _PFA_WIN_POS, 0x00000000, },
|
||||
{R, 1, "Enabled,PIPEA,Hardcoded edge enhance", _PFA_CTL_1, 0x80800000, },
|
||||
{V,0,},
|
||||
/* END SCALING HACK */
|
||||
#endif
|
||||
{R, 2, "", PCH_DP_D, 0x00000004, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000000, },
|
||||
{W, 1, "", _PIPEACONF, 0x00000040, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000040, },
|
||||
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:"},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],"
|
||||
"Modeline 0:\"2560x1700\" 60 285250 2560 2608 2640 2720 1700 1703 1713 1749"
|
||||
" 0x48 0xa"},
|
||||
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, },
|
||||
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, },
|
||||
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, },
|
||||
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, },
|
||||
{W, 1, "", _PCH_FPA1, 0x00020e08, },
|
||||
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, },
|
||||
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, },
|
||||
{W, 1, "", _HBLANK_A, 0x0a9f09ff, },
|
||||
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, },
|
||||
{W, 1, "", _VTOTAL_A, 0x06d406a3, },
|
||||
{W, 1, "", _VBLANK_A, 0x06d406a3, },
|
||||
{W, 1, "", _VSYNC_A, 0x06b006a6, },
|
||||
{W, 1, "", _PIPEASRC, 0x09ff06a3, },
|
||||
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, },
|
||||
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, },
|
||||
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, },
|
||||
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, },
|
||||
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000"},
|
||||
{R, 1, "", 0x64000, 0x0000001c, },
|
||||
{W, 1, "", 0x64000, 0x0000001c, },
|
||||
{R, 1, "", 0x64000, 0x0000001c, 500},
|
||||
{W, 1, "", _PIPEACONF, 0x00000050, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000050, },
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, },
|
||||
{W, 1, "", _PIPEASTAT, 0x00000002, },
|
||||
{R, 4562, "", _PIPEASTAT, 0x00000000, },
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
|
||||
{W, 1, "", _DSPACNTR, 0x40000000, },
|
||||
{R, 2, "", _DSPACNTR, 0x40000000, },
|
||||
{W, 1, "", _DSPACNTR, 0x58004000, },
|
||||
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240"},
|
||||
{W, 1, "", _DSPASTRIDE, 0x00002800, },
|
||||
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
|
||||
{W, 1, "", _DSPACNTR+0x24, 0x00000000, },
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, },
|
||||
{R, 1, "", _DSPACNTR, 0x58004000, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, },
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
|
||||
"cursor:6"},
|
||||
{W, 1, "", WM3_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM2_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM1_LP_ILK, 0x00000000, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
|
||||
"cursor 6"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM1_LP_ILK, 0x84302606, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1,"[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
|
||||
"cursor 6"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM2_LP_ILK, 0x90309106, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
|
||||
"cursor 10"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM3_LP_ILK, 0xa041200a, },
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]"
|
||||
"set [MODE:0:2560x1700]"},
|
||||
{M, 1, "[drm:ironlake_edp_pll_on], "},
|
||||
{R, 1, "", 0x64000, 0x0000001c, },
|
||||
{W, 1, "", 0x64000, 0x0000401c, },
|
||||
{R, 1, "", 0x64000, 0x0000401c, 200},
|
||||
{R, 1, "", 0x64000, 0x0000401c, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, },
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, },
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,"
|
||||
"cursor:6"},
|
||||
{W, 1, "", WM3_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM2_LP_ILK, 0x00000000, },
|
||||
{W, 1, "", WM1_LP_ILK, 0x00000000, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,"
|
||||
"cursor 6"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM1_LP_ILK, 0x84302606, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, fbc lines 3,"
|
||||
"cursor 6"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM2_LP_ILK, 0x90309106, },
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, fbc lines 4,"
|
||||
"cursor 10"},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, },
|
||||
{W, 1, "", WM3_LP_ILK, 0xa041200a, },
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00000040, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000050, },
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
|
||||
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, },
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, },
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, },
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, },
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, },
|
||||
{R, 1, "", _PIPEACONF, 0x00000050, },
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, },
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{P, 1, "Set palette", },
|
||||
{R, 1, "", _PIPEACONF, 0x00000050, },
|
||||
{W, 1, "", _PIPEACONF, 0x80000050, },
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, },
|
||||
{W, 1, "", _PIPEASTAT, 0x00000002, },
|
||||
{R, 4533, "", _PIPEASTAT, 0x00000000, },
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
|
||||
{R, 1, "", _PIPEACONF, 0xc0000050, },
|
||||
{R, 1, "", _DSPACNTR, 0x58004000, },
|
||||
{W, 1, "", _DSPACNTR, 0xd8004000, },
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, },
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, },
|
||||
{R, 1, "", _DSPASIZE+0xc, 0x00000000, },
|
||||
{W, 1, "", _DSPASIZE+0xc, 0x00000000, },
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, },
|
||||
{W, 1, "", _PIPEASTAT, 0x00000002, },
|
||||
{R, 4392, "", _PIPEASTAT, 0x00000000, },
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on"},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on"},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle"},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008"},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0008, },
|
||||
{W, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd000b, },
|
||||
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on"},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b"},
|
||||
{R, 4, "", PCH_PP_STATUS, 0x0000000a, },
|
||||
{R, 16983, "", PCH_PP_STATUS, 0x9000000a, },
|
||||
{R, 17839, "", PCH_PP_STATUS, 0x90000009, },
|
||||
{R, 1, "", PCH_PP_STATUS, 0x80000008, },
|
||||
//{V, 7,},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1"},
|
||||
{R, 2, "", PCH_PP_CONTROL, 0xabcd000b, },
|
||||
{W, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
|
||||
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003"},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{W, 1, "", 0x64000, 0x8e1c4104, },
|
||||
{R, 1, "", 0x64000, 0x8e1c4104, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", 0x64000, 0x8cdc4104, },
|
||||
{M, 1, "[drm:intel_dp_link_down], "},
|
||||
{W, 1, "", 0x64000, 0x8e1c0004, },
|
||||
{R, 1, "", 0x64000, 0x8e1c0004, 100},
|
||||
{W, 1, "", 0x64000, 0x8e1c0204, },
|
||||
{R, 1, "", 0x64000, 0x8e1c0204, },
|
||||
{W, 1, "", 0x64000, 0x0e1c0304, },
|
||||
{R, 2, "", 0x64000, 0x0e1c0304, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010008, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x0a840000, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA3, 0x00000000, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA4, 0x01000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd2d500c8, },
|
||||
{R, 3, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{W, 1, "", 0x64000, 0x891c4004, },
|
||||
{R, 1, "", 0x64000, 0x891c4004, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x21000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
|
||||
{R, 3, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 100},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00111180, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
|
||||
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK"},
|
||||
{W, 1, "", 0x64000, 0x891c4104, },
|
||||
{R, 1, "", 0x64000, 0x891c4104, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x22000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010303, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd28500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x800500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, 400},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x001500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x90020205, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd24500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x801500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x804500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x407500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x527500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00777781, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA2, 0x02000000, },
|
||||
{W, 1, "", 0x64000, 0x891c4304, },
|
||||
{R, 1, "", 0x64000, 0x891c4304, },
|
||||
{R, 2, "", PCH_PP_STATUS, 0x80000008, },
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x007500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA1, 0x80010200, },
|
||||
{W, 1, "", DPA_AUX_CH_DATA2, 0x00000000, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0xd25500c8, },
|
||||
{R, 2, "", DPA_AUX_CH_CTL, 0x807500c8, 100},
|
||||
{R, 1, "", DPA_AUX_CH_CTL, 0x401500c8, },
|
||||
{W, 1, "", DPA_AUX_CH_CTL, 0x521500c8, },
|
||||
{R, 1, "", DPA_AUX_CH_DATA1, 0x00000000, },
|
||||
{M, 1, "[drm:ironlake_edp_backlight_on], "},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0003, },
|
||||
{W, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
|
||||
{R, 1, "", PCH_PP_CONTROL, 0xabcd0007, },
|
||||
{R, 1, "", _PIPEADSL, 0x00000633, 500},
|
||||
{R, 1, "", _PIPEADSL, 0x00000652, },
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, },
|
||||
{W, 1, "", _PIPEASTAT, 0x00000002, },
|
||||
{R, 5085, "", _PIPEASTAT, 0x00000000, },
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out"},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4"
|
||||
"clock 270000"},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]"},
|
||||
{0,},
|
||||
};
|
||||
{V, 0},
|
||||
{W, 1, "", PCH_GMBUS0, 0x00000000, 0},
|
||||
{R, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x0 << 16) | ( /* T5 */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x0 << 16) | ( /* Tx */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", PP_ON_DELAYS, ( /* T2 */ 0x190 << 16) | ( /* T5 */ 0x7d0 << 0) | 0x019007d0, 0},
|
||||
{W, 1, "", PP_OFF_DELAYS, ( /* T3 */ 0x15e << 16) | ( /* Tx */ 0x7d0 << 0) | 0x015e07d0, 0},
|
||||
{M, 1, "[drm:intel_detect_pch], Found PatherPoint PCH", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:i915_load_modeset_init], failed to find VBIOS tables", 0x0, 0xcf8e64, 0},
|
||||
{R, 50, "", FORCEWAKE_MT_ACK, 0x00000001, 10},
|
||||
{W, 1, "", FORCEWAKE_MT, 0x00010001, 0},
|
||||
{R, 1, "", FORCEWAKE_MT, 0x00010001, 0},
|
||||
{R, 1, "", FORCEWAKE_MT_ACK, 0x00000001, 0},
|
||||
{R, 1, "", 0x13805c, 0x40000000, 0},
|
||||
{R, 1, "", 0xa180, 0x84100020, 0},
|
||||
{W, 1, "", FORCEWAKE_MT, 0x00010000, 0},
|
||||
{R, 1, "", 0x120000, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_init_display], Using MT version of forcewake", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:intel_modeset_init], 3 display pipes available.", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{R, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEBCONF, 0x00000000, 0},
|
||||
{R, 1, "", 0x72008, 0x00000000, 0},
|
||||
{W, 1, "", 0x72008, 0x00000000, 300},
|
||||
{W, 1, "", CPU_VGACNTRL, 0x80000000, 0},
|
||||
{R, 1, "", CPU_VGACNTRL, 0x80000000, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{R, 1, "", PCH_PP_ON_DELAYS, PANEL_PORT_SELECT_DPA | ( /* PANEL_POWER_UP_DELAY */ 0x7d0 << 16) | ( /* PANEL_LIGHT_ON_DELAY */ 0x7d0 << 0) | 0x47d007d0, 0},
|
||||
{R, 1, "", PCH_PP_OFF_DELAYS, ( /* PANEL_POWER_DOWN_DELAY */ 0x1f4 << 16) | ( /* PANEL_LIGHT_OFF_DELAY */ 0x7d0 << 0) | 0x01f407d0, 0},
|
||||
{R, 1, "", PCH_PP_DIVISOR, 0x00186906, 0},
|
||||
{M, 1, "[drm:intel_dp_init], cur t1_t3 2000 t8 2000 t9 2000 t10 500t11_t12 6000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], vbt t1_t3 0 t8 0 t9 0 t10 0 t11_t12 0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], panel power up delay 200,power down" "delay 50, power cycle delay 600", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_init], backlight on delay 200, off delay 200", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:00000000", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, 0x00000000, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], eDP was not running", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:intel_dp_i2c_init], i2c_init DPDDC-A", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", BLC_PWM_CPU_CTL, 0x000010ce, 0},
|
||||
{M, 1, "[drm:intel_panel_get_backlight], get backlight PWM = 4302", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5145003f", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_i2c_aux_ch], aux_ch failed -110", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], has_panel 1 has_lvds 0 " "has_pch_edp 0has_cpu_edp 1 has_ck505 0", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on panel", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00001402, 200},
|
||||
{M, 1, "[drm:ironlake_init_pch_refclk], Using SSC on eDP", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 0},
|
||||
{R, 1, "", PCH_DREF_CONTROL, DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD | DREF_SSC_SOURCE_ENABLE | DREF_NONSPREAD_SOURCE_ENABLE | DREF_SSC1_ENABLE | 0x00005402, 200},
|
||||
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", 0x9404, 0x00002000, 0},
|
||||
{W, 1, "", ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE | 0x10000000, 0},
|
||||
{W, 1, "", IVB_CHICKEN3, 0x00000024, 0},
|
||||
{W, 1, "", GEN7_COMMON_SLICE_CHICKEN1, 0x04000400, 0},
|
||||
{W, 1, "", 0xb01c, 0x3c4fff8c, 0},
|
||||
{W, 1, "", GEN7_L3_CHICKEN_MODE_REGISTER, 0x20000000, 0},
|
||||
{R, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000000, 0},
|
||||
{W, 1, "", GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0x00000800, 0},
|
||||
{R, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x00000000, 0},
|
||||
{W, 1, "", _DSPACNTR, ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x00004000, 0},
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{R, 1, "", _DSPBCNTR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBCNTR, 0x00004000, 0},
|
||||
{R, 1, "", _DSPBADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPBSURF, 0x00000000, 0},
|
||||
{W, 1, "", _DSPBSURF, 0x00000000, 0},
|
||||
{R, 1, "", _DVSACNTR, 0x00000000, 0},
|
||||
{W, 1, "", _DVSACNTR, DVS_TRICKLE_FEED_DISABLE | 0x00004000, 0},
|
||||
{R, 1, "", _DVSALINOFF, 0x00000000, 0},
|
||||
{W, 1, "", _DVSALINOFF, 0x00000000, 0},
|
||||
{R, 1, "", _DVSASURF, 0x00000000, 0},
|
||||
{W, 1, "", _DVSASURF, 0x00000000, 0},
|
||||
{W, 1, "", SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | 0x20000000, 0},
|
||||
{R, 1, "", SOUTH_CHICKEN2, 0x00000000, 0},
|
||||
{W, 1, "", SOUTH_CHICKEN2, DPLS_EDP_PPS_FIX_DIS | 0x00000001, 0},
|
||||
{W, 1, "", _TRANSA_CHICKEN2, 0x80000000, 0},
|
||||
{W, 1, "", _TRANSB_CHICKEN2, TRANS_AUTOTRAIN_GEN_STALL_DIS | 0x80000000, 0},
|
||||
{M, 1, "[drm:drm_edid_to_eld], ELD:no CEA Extension found", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], " "[CONNECTOR:6:eDP-1]probed modes :", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 17490x48 0xa", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], ", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], picking CRTCs for 8192x8192 config", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_setup_crtcs], desired mode 2560x1700 set on crtc 3", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:6:eDP-1]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_detect], DPCD:110a8441000001c0", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_enable_connectors], connector 6 enabled? yes", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_get_load_detect_pipe], [CONNECTOR:6:eDP-1],[ENCODER:7:TMDS-7]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{I,},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_DP_D, 0x00000004, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_8 | PIPECONF_DITHER_TYPE_SP | 0x00000000, 0},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_TYPE_SP | 0x00000040, 0},
|
||||
{M, 1, "[drm:ironlake_crtc_mode_set], Mode for pipe 0:", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_mode_debug_printmodeline],Modeline 0:\"2560x1700\" " "60 285250 2560 2608 2640 2720 1700 1703 1713 1749 0x48 0xa", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _TRANSA_DATA_M1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DATA_N1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DP_LINK_M1, 0x00000000, 0},
|
||||
{W, 1, "", _TRANSA_DP_LINK_N1, 0x00000000, 0},
|
||||
{W, 1, "", _PCH_FPA1, 0x00020e08, 0},
|
||||
{W, 1, "", _VSYNCSHIFT_A, 0x00000000, 0},
|
||||
{W, 1, "", _HTOTAL_A, 0x0a9f09ff, 0},
|
||||
{W, 1, "", _HBLANK_A, 0x0a9f09ff, 0},
|
||||
{W, 1, "", _HSYNC_A, 0x0a4f0a2f, 0},
|
||||
{W, 1, "", _VTOTAL_A, 0x06d406a3, 0},
|
||||
{W, 1, "", _VBLANK_A, 0x06d406a3, 0},
|
||||
{W, 1, "", _VSYNC_A, 0x06b006a6, 0},
|
||||
{W, 1, "", _PIPEASRC, 0x09ff06a3, 0},
|
||||
{W, 1, "", _PIPEA_DATA_M1, 0x7e4e58a4, 0},
|
||||
{W, 1, "", _PIPEA_DATA_N1, 0x0083d600, 0},
|
||||
{W, 1, "", _PIPEA_LINK_M1, 0x00045a42, 0},
|
||||
{W, 1, "", _PIPEA_LINK_N1, 0x00041eb0, 0},
|
||||
{M, 1, "[drm:ironlake_set_pll_edp], eDP PLL enable for clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 500},
|
||||
{W, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4562, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
|
||||
{R, 2, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | 0x40000000, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{M, 1, "[drm:ironlake_update_plane], Writing base 00000000 00000000 0 0 10240", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", _DSPASTRIDE, 0x00002800, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPACNTR + 0x24, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00783818, 0},
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) | ( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane " "288, fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) | ( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7]set [MODE:0:2560x1700]", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_pll_on], ", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000001c, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 200},
|
||||
{R, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_SYNC_VS_HIGH | DP_SYNC_HS_HIGH | DP_DETECTED | 0x0000401c, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{R, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{W, 1, "", WM0_PIPEA_ILK, 0x00183806, 0},
|
||||
{M, 1, "[drm:sandybridge_update_wm], FIFO watermarks For pipe A - plane 24,cursor:6", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", WM3_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM2_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{W, 1, "", WM1_LP_ILK, ( /* WMx_LP_LATENCY */ 0x0 << 24) | ( /* WMx_LP_FBC */ 0x0 << 20) | ( /* WMx_LP_SR */ 0x0 << 8) | ( /* WMx_LP_CURSOR */ 0x0 << 0) | 0x00000000, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 1:display plane 38, fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM1_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x4 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x26 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x84302606, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 2:display plane 145, " "fbc lines 3,cursor 6", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM2_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x10 << 24) | ( /* WMx_LP_FBC */ 0x3 << 20) |( /* WMx_LP_SR */ 0x91 << 8) | ( /* WMx_LP_CURSOR */ 0x6 << 0) | 0x90309106, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{M, 1, "[drm:ironlake_check_srwm], watermark 3:display plane 288, " "fbc lines 4,cursor 10", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", 0x145d10, 0x2010040c, 0},
|
||||
{W, 1, "", WM3_LP_ILK, WMx_LP_SR_EN | ( /* WMx_LP_LATENCY */ 0x20 << 24) | ( /* WMx_LP_FBC */ 0x4 << 20) |( /* WMx_LP_SR */ 0x120 << 8) | ( /* WMx_LP_CURSOR */ 0xa << 0) | 0xa041200a, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00000040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{W, 2, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{R, 1, "", SOUTH_CHICKEN1, 0x00000000, 0},
|
||||
{R, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{W, 1, "", _FDI_TXA_CTL, 0x00040000, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _FDI_RXA_CTL, 0x00020040, 0},
|
||||
{R, 1, "", _FDI_RXA_CTL, 0x00020040, 100},
|
||||
{P, 1, "Set Palette"},
|
||||
{R, 1, "", _PIPEACONF, ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x00000050, 0},
|
||||
{W, 1, "", _PIPEACONF, PIPECONF_ENABLE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP | 0x80000050, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4533, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", _PIPEACONF, PIPECONF_ENABLE | PIPECONF_DOUBLE_WIDE | ( /* PIPECONF_FRAME_START_DELAY_MASK */ 0x0 << 27) | PIPECONF_BPP_6 | PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP |0xc0000050, 0},
|
||||
{R, 1, "", _DSPACNTR, DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0x58004000, 0},
|
||||
{W, 1, "", _DSPACNTR, DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE | (DISPPLANE_32BPP_NO_ALPHA & 0x18000000) | ( /* DISPPLANE_SEL_PIPE(0=A,1=B) */ 0x0 << 24) | DISPPLANE_TRICKLE_FEED_DISABLE /* Ironlake */ | 0xd8004000, 0},
|
||||
{R, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{W, 1, "", _DSPAADDR, 0x00000000, 0},
|
||||
{R, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{W, 1, "", _DSPASIZE + 0xc, 0x00000000, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 4392, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_on], Turn eDP VDD on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_on], Turn eDP power on", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_power_cycle], Wait for panel power cycle", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd0008", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | 0xabcd0008, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_on], Wait for panel power on", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:ironlake_wait_panel_status], R PCH_PP_CONTROL:abcd000b", 0x0, 0xcf8e64, 0},
|
||||
{R, 4, "", PCH_PP_STATUS, /*undocbit3 | undocbit1 | */ 0x0000000a, 0},
|
||||
{R, 16983, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit1 | */ 0x9000000a, 0},
|
||||
{R, 17839, "", PCH_PP_STATUS, PP_ON | PP_SEQUENCE_POWER_UP | /*undocbit3 | undocbit0 | */ 0x90000009, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{M, 1, "[drm:ironlake_edp_panel_vdd_off], Turn eDP VDD off 1", 0x0, 0xcf8e64, 0},
|
||||
{R, 2, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_FORCE_VDD | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd000b, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{M, 1, "[drm:ironlake_panel_vdd_off_sync], R PCH_PP_CONTROL:abcd0003", 0x0, 0xcf8e64, 0},
|
||||
{R, 1, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8e1c4104, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PRE_EMPHASIS_9_5 & 0xc00000) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x8cdc4104, 0},
|
||||
{M, 1, "[drm:intel_dp_link_down], ", 0x0, 0xcf8e64, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0004, 100},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_IDLE_CPT | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x8e1c0204, 0},
|
||||
{W, 1, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
|
||||
{R, 2, "", DP_A, DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | DP_PRE_EMPHASIS_0 | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_DETECTED | 0x0e1c0304, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4004, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /*undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:intel_dp_start_link_train], clock recovery OK", 0x0, 0x00000000, 0},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_2_CPT | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4104, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{W, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
|
||||
{R, 1, "", DP_A, DP_PORT_EN | DP_LINK_TRAIN_PAT_1 | (DP_LINK_TRAIN_OFF_CPT & 0x300) | (DP_PORT_WIDTH_4 & 0x180000) | DP_ENHANCED_FRAMING | DP_PLL_FREQ_270MHZ | DP_PLL_ENABLE | DP_DETECTED | 0x891c4304, 0},
|
||||
{R, 2, "", PCH_PP_STATUS, PP_ON | /* undocbit3 | */ 0x80000008, 0},
|
||||
{I,},
|
||||
{M, 1, "[drm:ironlake_edp_backlight_on], ", 0x0, 0x00000000, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0003, 0},
|
||||
{W, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
|
||||
{R, 1, "", PCH_PP_CONTROL, (PCH_PP_UNLOCK & 0xabcd0000) | EDP_BLC_ENABLE | PANEL_POWER_RESET | PANEL_POWER_ON | 0xabcd0007, 0},
|
||||
{R, 1, "", _PIPEADSL, 0x00000633, 500},
|
||||
{R, 1, "", _PIPEADSL, 0x00000652, 0},
|
||||
{R, 1, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{W, 1, "", _PIPEASTAT, PIPE_VBLANK_INTERRUPT_STATUS | 0x00000002, 0},
|
||||
{R, 5085, "", _PIPEASTAT, 0x00000000, 0},
|
||||
{M, 1, "[drm:intel_wait_for_vblank], vblank wait timed out", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:intel_dp_mode_fixup], Display port link bw 0a lane count 4clock 270000", 0x0, 0xcf8e64, 0},
|
||||
{M, 1, "[drm:drm_crtc_helper_set_mode], [CRTC:3]", 0x0, 0xcf8e64, 0},
|
||||
{I, 0, "(null)", 0x0, 0xcf8e64, 0}, };
|
||||
|
||||
int niodefs = sizeof (iodefs) / sizeof (iodefs[0]);
|
||||
|
|
|
|||
|
|
@ -18,6 +18,21 @@
|
|||
*/
|
||||
|
||||
#include "i915_reg.h"
|
||||
#include "drm_dp_helper.h"
|
||||
|
||||
/* things that are, strangely, not defined anywhere? */
|
||||
#define PCH_PP_UNLOCK 0xabcd0000
|
||||
#define WMx_LP_SR_EN (1<<31)
|
||||
|
||||
/* Google Link-specific defines */
|
||||
/* how many 4096-byte pages do we need for the framebuffer?
|
||||
* There are 32 bits per pixel, or 4 bytes,
|
||||
* which means 1024 pixels per page.
|
||||
* HencetThere are 4250 GTTs on Link:
|
||||
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
|
||||
*/
|
||||
#define FRAME_BUFFER_PAGES ((2560*1700)/1024)
|
||||
#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096)
|
||||
|
||||
/* One-letter commands for code not meant to be ready for humans.
|
||||
* The code was generated by a set of programs/scripts.
|
||||
|
|
@ -46,10 +61,10 @@
|
|||
*/
|
||||
#define M 1
|
||||
#define R 2
|
||||
#define W 3
|
||||
#define V 4
|
||||
#define I 8
|
||||
#define P 16
|
||||
#define W 4
|
||||
#define V 8
|
||||
#define I 16
|
||||
#define P 32
|
||||
|
||||
struct iodef {
|
||||
unsigned char op;
|
||||
|
|
@ -65,8 +80,8 @@ unsigned long io_i915_READ32(unsigned long addr);
|
|||
void io_i915_WRITE32(unsigned long val, unsigned long addr);
|
||||
|
||||
/* intel_dp.c */
|
||||
u32 pack_aux(u8 *src, int src_bytes);
|
||||
void unpack_aux(u32 src, u8 *dst, int dst_bytes);
|
||||
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
|
||||
u8 *recv, int recv_size);
|
||||
u32 pack_aux(u32 *src, int src_bytes);
|
||||
void unpack_aux(u32 src, u32 *dst, int dst_bytes);
|
||||
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size);
|
||||
|
||||
|
|
|
|||
|
|
@ -32,8 +32,9 @@
|
|||
#include "i915io.h"
|
||||
|
||||
u32
|
||||
pack_aux(u8 *src, int src_bytes)
|
||||
pack_aux(u32 *src32, int src_bytes)
|
||||
{
|
||||
u8 *src = (u8 *)src32;
|
||||
int i;
|
||||
u32 v = 0;
|
||||
|
||||
|
|
@ -45,8 +46,10 @@ pack_aux(u8 *src, int src_bytes)
|
|||
}
|
||||
|
||||
void
|
||||
unpack_aux(u32 src, u8 *dst, int dst_bytes)
|
||||
unpack_aux(u32 src, u32 *dst32, int dst_bytes)
|
||||
{
|
||||
u8 *dst = (u8 *)dst32;
|
||||
|
||||
int i;
|
||||
if (dst_bytes > 4)
|
||||
dst_bytes = 4;
|
||||
|
|
@ -55,8 +58,8 @@ unpack_aux(u32 src, u8 *dst, int dst_bytes)
|
|||
}
|
||||
|
||||
int
|
||||
intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
|
||||
u8 *recv, int recv_size)
|
||||
intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
|
||||
u32 *recv, int recv_size)
|
||||
{
|
||||
int i;
|
||||
int recv_bytes;
|
||||
|
|
@ -93,11 +96,10 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
|
|||
for (try = 0; try < 5; try++) {
|
||||
/* Load the send data into the aux channel data registers */
|
||||
for (i = 0; i < send_bytes; i += 4)
|
||||
io_i915_WRITE32(ch_data + i,
|
||||
pack_aux(send + i, send_bytes - i));
|
||||
io_i915_WRITE32(send[i], ch_data + i);
|
||||
|
||||
/* Send the command and wait for it to complete */
|
||||
io_i915_WRITE32(ch_ctl,
|
||||
io_i915_WRITE32(
|
||||
DP_AUX_CH_CTL_SEND_BUSY |
|
||||
DP_AUX_CH_CTL_TIME_OUT_400us |
|
||||
(send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
|
||||
|
|
@ -105,7 +107,7 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
|
|||
(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR);
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
for (;;) {
|
||||
status = io_i915_READ32(ch_ctl);
|
||||
if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
|
||||
|
|
@ -114,11 +116,11 @@ intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u8 *send, int send_bytes,
|
|||
}
|
||||
|
||||
/* Clear done status and any errors */
|
||||
io_i915_WRITE32(ch_ctl,
|
||||
io_i915_WRITE32(
|
||||
status |
|
||||
DP_AUX_CH_CTL_DONE |
|
||||
DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR);
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR, ch_ctl);
|
||||
|
||||
if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
|
||||
DP_AUX_CH_CTL_RECEIVE_ERROR))
|
||||
|
|
|
|||
Loading…
Reference in New Issue