arch/x86: Add <arch/romstage.h>

Start with moving all postcar_frame related function
declarations here from <arch/cpu.h>.

Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/arch/x86/include/arch/cpu.h

@@ -279,11 +279,10 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
 		c->x86_model += ((tfms >> 16) & 0xF) << 4;
 
 }
-#endif
 
+/* romcc does not understand regparm. */
 #define asmlinkage __attribute__((regparm(0)))
 
-#ifndef __ROMCC__
 /*
  * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry()
  * is the symbol jumped to for each stage after bootblock using
@@ -291,66 +290,6 @@ static inline void get_fms(struct cpuinfo_x86 *c, uint32_t tfms)
  */
 asmlinkage void car_stage_entry(void);
 
-/*
- * Support setting up a stack frame consisting of MTRR information
- * for use in bootstrapping the caching attributes after cache-as-ram
- * is torn down.
- */
-
-struct postcar_frame {
-	uintptr_t stack;
-	uint32_t upper_mask;
-	int max_var_mtrrs;
-	int num_var_mtrrs;
-	int skip_common_mtrr;
-};
-
-/*
- * Initialize postcar_frame object allocating stack from cbmem,
- * with stack_size == 0, default 4 KiB is allocated.
- * Returns 0 on success, < 0 on error.
- */
-int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
-
-/*
- * Add variable MTRR covering the provided range with MTRR type.
- */
-void postcar_frame_add_mtrr(struct postcar_frame *pcf,
-				uintptr_t addr, size_t size, int type);
-
-/*
- * Add variable MTRR covering the memory-mapped ROM with given MTRR type.
- */
-void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
-
-/*
- * Add a common MTRR setup most platforms will have as a subset.
- */
-void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
-
-/*
- * Push used MTRR and Max MTRRs on to the stack
- * and return pointer to stack top.
- */
-void *postcar_commit_mtrrs(struct postcar_frame *pcf);
-
-/*
- * Load and run a program that takes control of execution that
- * tears down CAR and loads ramstage. The postcar_frame object
- * indicates how to set up the frame. If caching is enabled at
- * the time of the call it is up to the platform code to handle
- * coherency with dirty lines in the cache using some mechansim
- * such as platform_prog_run() because run_postcar_phase()
- * utilizes prog_run() internally.
- */
-void run_postcar_phase(struct postcar_frame *pcf);
-
-/*
- * Systems without a native coreboot cache-as-ram teardown may implement
- * this to use an alternate method.
- */
-void late_car_teardown(void);
-
 #endif
 
 /*

src/arch/x86/include/arch/romstage.h

@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ROMSTAGE_H__
+#define __ARCH_ROMSTAGE_H__
+
+#include <arch/cpu.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * Support setting up a stack frame consisting of MTRR information
+ * for use in bootstrapping the caching attributes after cache-as-ram
+ * is torn down.
+ */
+
+struct postcar_frame {
+	uintptr_t stack;
+	uint32_t upper_mask;
+	int max_var_mtrrs;
+	int num_var_mtrrs;
+	int skip_common_mtrr;
+};
+
+/*
+ * Initialize postcar_frame object allocating stack from cbmem,
+ * with stack_size == 0, default 4 KiB is allocated.
+ * Returns 0 on success, < 0 on error.
+ */
+int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size);
+
+/*
+ * Add variable MTRR covering the provided range with MTRR type.
+ */
+void postcar_frame_add_mtrr(struct postcar_frame *pcf,
+				uintptr_t addr, size_t size, int type);
+
+/*
+ * Add variable MTRR covering the memory-mapped ROM with given MTRR type.
+ */
+void postcar_frame_add_romcache(struct postcar_frame *pcf, int type);
+
+/*
+ * Add a common MTRR setup most platforms will have as a subset.
+ */
+void postcar_frame_common_mtrrs(struct postcar_frame *pcf);
+
+/*
+ * Push used MTRR and Max MTRRs on to the stack
+ * and return pointer to stack top.
+ */
+void *postcar_commit_mtrrs(struct postcar_frame *pcf);
+
+/*
+ * Load and run a program that takes control of execution that
+ * tears down CAR and loads ramstage. The postcar_frame object
+ * indicates how to set up the frame. If caching is enabled at
+ * the time of the call it is up to the platform code to handle
+ * coherency with dirty lines in the cache using some mechansim
+ * such as platform_prog_run() because run_postcar_phase()
+ * utilizes prog_run() internally.
+ */
+void run_postcar_phase(struct postcar_frame *pcf);
+
+/*
+ * Systems without a native coreboot cache-as-ram teardown may implement
+ * this to use an alternate method.
+ */
+void late_car_teardown(void);
+
+#endif /* __ARCH_ROMSTAGE_H__ */

src/arch/x86/postcar.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>

src/arch/x86/postcar_loader.c

@@ -13,7 +13,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/cpu.h>

src/cpu/intel/car/romstage.c

@@ -11,6 +11,8 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <bootblock_common.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/drivers/amd/agesa/mtrr_fixme.c

@@ -11,7 +11,7 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <commonlib/helpers.h>

src/drivers/amd/agesa/romstage.c

@@ -15,6 +15,7 @@
 
 #include <arch/acpi.h>
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <cpu/amd/car.h>
 #include <cpu/x86/bist.h>

src/drivers/intel/fsp1_1/car.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/romstage.h>
 #include <arch/symbols.h>
 #include <cbmem.h>
 #include <console/console.h>

src/drivers/intel/fsp2_0/temp_ram_exit.c

@@ -9,7 +9,7 @@
  * (at your option) any later version.
  */
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <console/console.h>
 #include <fsp/api.h>
 #include <fsp/util.h>

src/include/cpu/intel/romstage.h

@@ -1,7 +1,7 @@
 #ifndef _CPU_INTEL_ROMSTAGE_H
 #define _CPU_INTEL_ROMSTAGE_H
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 
 void mainboard_romstage_entry(void);
 

src/mainboard/emulation/qemu-i440fx/romstage.c

@@ -15,10 +15,10 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <stdint.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <timestamp.h>
 #include <program_loading.h>
 

src/mainboard/emulation/qemu-q35/romstage.c

@@ -15,10 +15,10 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <stdint.h>
 #include <cbmem.h>
 #include <console/console.h>
-#include <cpu/intel/romstage.h>
 #include <timestamp.h>
 #include <southbridge/intel/i82801ix/i82801ix.h>
 #include <program_loading.h>

src/northbridge/amd/agesa/agesa_helper.h

@@ -17,7 +17,7 @@
 #define _AGESA_HELPER_H_
 
 #include <stddef.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 
 enum {
 	PICK_DMI,       /* DMI Interface */

src/northbridge/intel/e7505/memmap.c

@@ -15,7 +15,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <device/pci_ops.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>

src/northbridge/intel/gm45/memmap.c

@@ -18,7 +18,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <stdint.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>

src/northbridge/intel/haswell/memmap.c

@@ -16,7 +16,7 @@
 // Use simple device model for this file even in ramstage
 #define __SIMPLE_DEVICE__
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>
 #include <device/pci_ops.h>

src/northbridge/intel/i440bx/memmap.c

@@ -15,7 +15,7 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>

src/northbridge/intel/i945/memmap.c

@@ -17,7 +17,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <device/pci_ops.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cbmem.h>
 #include "i945.h"
 #include <console/console.h>

src/northbridge/intel/nehalem/memmap.c

@@ -16,7 +16,7 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>

src/northbridge/intel/pineview/memmap.c

@@ -16,7 +16,7 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>

src/northbridge/intel/sandybridge/memmap.c

@@ -15,7 +15,7 @@
 
 #define __SIMPLE_DEVICE__
 
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
 #include <console/console.h>

src/northbridge/intel/x4x/memmap.c

@@ -20,7 +20,7 @@
 #include <cbmem.h>
 #include <commonlib/helpers.h>
 #include <stdint.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
 #include <console/console.h>

src/soc/amd/picasso/romstage.c

@@ -16,6 +16,7 @@
 
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/soc/amd/stoneyridge/romstage.c

@@ -16,6 +16,7 @@
 
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/acpi.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/soc/intel/apollolake/romstage.c

@@ -17,6 +17,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <device/pci_ops.h>
 #include <arch/symbols.h>
 #include <assert.h>

src/soc/intel/baytrail/romstage/romstage.c

@@ -16,6 +16,7 @@
 #include <stddef.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
+#include <arch/romstage.h>
 #include <device/mmio.h>
 #include <device/pci_ops.h>
 #include <bootblock_common.h>

src/soc/intel/broadwell/romstage/romstage.c

@@ -16,7 +16,7 @@
 #include <stddef.h>
 #include <stdint.h>
 #include <arch/cbfs.h>
-#include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <bootblock_common.h>
 #include <bootmode.h>
 #include <cbmem.h>

src/soc/intel/cannonlake/romstage/romstage.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>

src/soc/intel/denverton_ns/romstage.c

@@ -15,6 +15,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <cf9_reset.h>

src/soc/intel/icelake/romstage/romstage.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <cbmem.h>
 #include <console/console.h>

src/soc/intel/quark/romstage/fsp2_0.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/symbols.h>
 #include <console/console.h>
 #include <cbmem.h>

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -14,6 +14,7 @@
  */
 
 #include <arch/cpu.h>
+#include <arch/romstage.h>
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cpu/x86/mtrr.h>