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soc/intel/cannonlake: Port SD Controller W/A from Intel Reference code 

Solution: To do an additional config read to the SD controller
after the controller has been power gated (put to D3)

Change-Id: Ia2438c767332b0e2d413c71b06b052bf9ab4a96c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Subrata Banik 2018-01-18 15:20:21 +05:30
parent d99f9d526f
commit a971254d67
1 changed files with 13 additions and 2 deletions
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15
src/soc/intel/cannonlake/acpi/scs.asl
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@ -51,23 +51,34 @@ Scope (\_SB.PCI0) {
Device (SDXC) Device (SDXC)
{ {
Name (_ADR, 0x00140005) Name (_ADR, 0x00140005)
Name (TEMP, 0)
OperationRegion (SDPC, PCI_Config, 0x00, 0x100) OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
Field (SDPC, WordAcc, NoLock, Preserve) Field (SDPC, WordAcc, NoLock, Preserve)
{ {
Offset(0xA2), /* Device Power Gate config */ Offset (0x84), /* PMECTRLSTATUS */
PMCR, 16,
Offset (0xA2), /* PG_CONFIG */
, 2, , 2,
PGEN, 1 /* PGE - PG Enable */ PGEN, 1, /* PG_ENABLE */
} }
Method (_PS0, 0, Serialized) Method (_PS0, 0, Serialized)
{ {
Store (0, PGEN) /* Disable PG */ Store (0, PGEN) /* Disable PG */
/* Set Power State to D0 */
And (PMCR, 0xFFFC, PMCR)
Store (PMCR, ^TEMP)
} }
Method (_PS3, 0, Serialized) Method (_PS3, 0, Serialized)
{ {
Store (1, PGEN) /* Enable PG */ Store (1, PGEN) /* Enable PG */
/* Set Power State to D3 */
Or (PMCR, 0x0003, PMCR)
Store (PMCR, ^TEMP)
} }
} /* Device (SDXC) */ } /* Device (SDXC) */
} }