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vendorcode/mediatek/mt8192: Fix set but unused variables 

The binary does change on these with BUILD_TIMELESS.

Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans 2023-04-18 20:08:46 +02:00 committed by Lean Sheng Tan
parent 7d6362d56b
commit a9737abf78
1 changed files with 11 additions and 36 deletions
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47
src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c
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@ -2949,7 +2949,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
{ {
U8 u1FinalVref, u1FinalRange=0; U8 u1FinalVref, u1FinalRange=0;
S8 iFinalCACLK; S8 iFinalCACLK;
U32 uiCAWinSumMax;
U8 operating_fsp; U8 operating_fsp;
U16 operation_frequency; U16 operation_frequency;
#if CA_PER_BIT_DELAY_CELL #if CA_PER_BIT_DELAY_CELL
@ -2962,12 +2961,11 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
S16 pi_step; S16 pi_step;
S16 pi_start, pi_end; S16 pi_start, pi_end;
u32 ca_ui, ca_ui_default; u32 ca_ui;
u32 ca_mck; u32 ca_mck;
u32 ca_cmd0; u32 ca_cmd0;
u8 ca_pin_num; u8 ca_pin_num;
u16 p2u; u16 p2u;
u8 step_respi = AUTOK_RESPI_1;
U32 u4RegBackupAddress[] = U32 u4RegBackupAddress[] =
{ {
@ -3016,12 +3014,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
break; break;
default: default:
/* LPDDR4 */
if (u1IsPhaseMode(p) == TRUE)
{
step_respi = AUTOK_RESPI_8;
}
#if CBT_MOVE_CA_INSTEAD_OF_CLK #if CBT_MOVE_CA_INSTEAD_OF_CLK
pi_start = -16; pi_start = -16;
pi_end = p2u * 3 - 1; pi_end = p2u * 3 - 1;
@ -3113,9 +3105,10 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
#endif #endif
/* read ca ui and mck */ /* read ca ui and mck */
ca_ui_default = ca_ui = get_ca_ui(p); ca_ui = get_ca_ui(p);
ca_mck = get_ca_mck(p); ca_mck = get_ca_mck(p);
ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0)); ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0));
(void)ca_cmd0;
vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable
@ -3139,9 +3132,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0), vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0),
1, TX_SET0_TXRANKFIX); 1, TX_SET0_TXRANKFIX);
//SW variable initialization
uiCAWinSumMax = 0;
iFinalCACLK = 0; iFinalCACLK = 0;
operating_fsp = p->dram_fsp; operating_fsp = p->dram_fsp;
operation_frequency = p->frequency; operation_frequency = p->frequency;
@ -3632,7 +3622,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
// Note that below procedure is based on "ODT off" // Note that below procedure is based on "ODT off"
DRAM_STATUS_T KResult = DRAM_FAIL; DRAM_STATUS_T KResult = DRAM_FAIL;
U8 byte_i, rank_i, ucDoneFlg; U8 byte_i, rank_i, ucDoneFlg = 0;
DRAM_RANK_T backup_rank; DRAM_RANK_T backup_rank;
S32 wrlevel_dqs_delay[DQS_NUMBER]; // 3 is channel number S32 wrlevel_dqs_delay[DQS_NUMBER]; // 3 is channel number
@ -6514,6 +6504,7 @@ U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p)
REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN}; REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN};
REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE}; REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE};
u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg); u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg);
(void)u4Response;
// Read RDDQC compare result // Read RDDQC compare result
u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP)); u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP));
@ -6538,14 +6529,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
u8 isAutoK) u8 isAutoK)
{ {
U8 u1BitIdx, u1ByteIdx; U8 u1BitIdx, u1ByteIdx;
U16 u16DelayStep = 1;
PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM]; PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM];
S32 iDQSDlyPerbyte[DQS_NUMBER], iDQMDlyPerbyte[DQS_NUMBER];//, iFinalDQSDly[DQS_NUMBER]; S32 iDQSDlyPerbyte[DQS_NUMBER], iDQMDlyPerbyte[DQS_NUMBER];//, iFinalDQSDly[DQS_NUMBER];
U8 u1VrefScanEnable = FALSE; U8 u1VrefScanEnable = FALSE;
U16 u2FinalVref [DQS_NUMBER]= {0xe, 0xe}; U16 u2FinalVref [DQS_NUMBER]= {0xe, 0xe};
U16 u2VrefBegin, u2VrefEnd, u2VrefStep; U16 u2VrefBegin, u2VrefEnd, u2VrefStep;
U8 u1RXEyeScanEnable=0,u1PrintCalibrationProc; U8 u1RXEyeScanEnable=0;
U8 u1CalDQMNum = 0;
#if ENABLE_EYESCAN_GRAPH #if ENABLE_EYESCAN_GRAPH
U8 EyeScan_index[DQ_DATA_WIDTH_LP4 + RDDQC_ADD_DMI_NUM] = {0}; U8 EyeScan_index[DQ_DATA_WIDTH_LP4 + RDDQC_ADD_DMI_NUM] = {0};
@ -6580,14 +6569,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
#if (FEATURE_RDDQC_K_DMI == TRUE) #if (FEATURE_RDDQC_K_DMI == TRUE)
if (u1UseTestEngine == PATTERN_RDDQC) if (u1UseTestEngine == PATTERN_RDDQC)
{ {
u1CalDQMNum = 2;
iDQMDlyPerbyte[0] = -0xFFFFFF; iDQMDlyPerbyte[0] = -0xFFFFFF;
iDQMDlyPerbyte[1] = -0xFFFFFF; iDQMDlyPerbyte[1] = -0xFFFFFF;
} }
else else
#endif #endif
{ {
u1CalDQMNum = 0;
iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0); iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0);
iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1); iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1);
@ -6650,7 +6637,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
u2VrefEnd = 0; u2VrefEnd = 0;
u2VrefStep = 1; u2VrefStep = 1;
if ((u1UseTestEngine == PATTERN_TEST_ENGINE)) if (u1UseTestEngine == PATTERN_TEST_ENGINE)
{ {
#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0) #if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1)) if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1))
@ -6660,8 +6647,6 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
#endif #endif
} }
u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL));
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
{ {
@ -6753,10 +6738,8 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
u2VrefEnd = 0; u2VrefEnd = 0;
u2VrefStep = 1; u2VrefStep = 1;
} }
(void)u2VrefStep;
//if RDDQD, roughly calibration
if (u1UseTestEngine == PATTERN_RDDQC)
u16DelayStep <<= 1;
#if SUPPORT_SAVE_TIME_FOR_CALIBRATION #if SUPPORT_SAVE_TIME_FOR_CALIBRATION
if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE))) if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
@ -7270,9 +7253,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val)
static U8 aru1RxDatlatResult[RANK_MAX]; static U8 aru1RxDatlatResult[RANK_MAX];
DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p) DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
{ {
U32 u4prv_register_080; U8 ucbest_step;
U8 ucfirst, ucbegin, ucsum, ucbest_step;
U16 u2DatlatBegin;
// error handling // error handling
if (!p) if (!p)
@ -7286,7 +7267,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
// pre-save // pre-save
// 0x07c[6:4] DATLAT bit2-bit0 // 0x07c[6:4] DATLAT bit2-bit0
u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT)); u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT));
//default set FAIL //default set FAIL
vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL); vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL);
@ -7302,12 +7284,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
// 4.set DATLAT 2nd value for optimal // 4.set DATLAT 2nd value for optimal
// Initialize // Initialize
ucfirst = 0xff;
ucbegin = 0;
ucsum = 0;
DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1 DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
u2DatlatBegin = 0;
#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT) #if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT)
if (p->femmc_Ready == 1) if (p->femmc_Ready == 1)
@ -9352,9 +9330,6 @@ void DramcTxOECalibration(DRAMC_CTX_T *p)
//U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step; //U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step;
U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0}; U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0};
//U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff; //U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff;
U8 u1TxDQOEShift = 0;
u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
#if TX_OE_PATTERN_USE_TA2 #if TX_OE_PATTERN_USE_TA2
msg("\n[DramC_TX_OE_Calibration] TA2\n"); msg("\n[DramC_TX_OE_Calibration] TA2\n");