vendorcode/mediatek/mt8192: Fix set but unused variables
The binary does change on these with BUILD_TIMELESS. Change-Id: I45d51d53f991556cedd1cc45997d76fc828bceb5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74544 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Arthur Heymans
Lean Sheng Tan
parent
7d6362d56b
commit
a9737abf78
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@ -2949,7 +2949,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
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{
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U8 u1FinalVref, u1FinalRange=0;
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S8 iFinalCACLK;
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U32 uiCAWinSumMax;
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U8 operating_fsp;
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U16 operation_frequency;
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#if CA_PER_BIT_DELAY_CELL
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@ -2962,12 +2961,11 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
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S16 pi_step;
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S16 pi_start, pi_end;
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u32 ca_ui, ca_ui_default;
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u32 ca_ui;
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u32 ca_mck;
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u32 ca_cmd0;
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u8 ca_pin_num;
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u16 p2u;
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u8 step_respi = AUTOK_RESPI_1;
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U32 u4RegBackupAddress[] =
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{
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@ -3016,12 +3014,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
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break;
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default:
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/* LPDDR4 */
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if (u1IsPhaseMode(p) == TRUE)
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{
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step_respi = AUTOK_RESPI_8;
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}
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#if CBT_MOVE_CA_INSTEAD_OF_CLK
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pi_start = -16;
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pi_end = p2u * 3 - 1;
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@ -3113,9 +3105,10 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
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#endif
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/* read ca ui and mck */
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ca_ui_default = ca_ui = get_ca_ui(p);
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ca_ui = get_ca_ui(p);
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ca_mck = get_ca_mck(p);
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ca_cmd0 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_CA_CMD0));
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(void)ca_cmd0;
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vAutoRefreshSwitch(p, DISABLE); //When doing CA training, should make sure that auto refresh is disable
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@ -3139,9 +3132,6 @@ DRAM_STATUS_T CmdBusTrainingLP45(DRAMC_CTX_T *p, int autok)
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vIO32WriteFldAlign(DRAMC_REG_ADDR(DRAMC_REG_TX_SET0),
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1, TX_SET0_TXRANKFIX);
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//SW variable initialization
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uiCAWinSumMax = 0;
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iFinalCACLK = 0;
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operating_fsp = p->dram_fsp;
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operation_frequency = p->frequency;
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@ -3632,7 +3622,7 @@ DRAM_STATUS_T DramcWriteLeveling(DRAMC_CTX_T *p, u8 isAutoK, WLEV_DELAY_BASED_T
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// Note that below procedure is based on "ODT off"
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DRAM_STATUS_T KResult = DRAM_FAIL;
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U8 byte_i, rank_i, ucDoneFlg;
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U8 byte_i, rank_i, ucDoneFlg = 0;
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DRAM_RANK_T backup_rank;
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S32 wrlevel_dqs_delay[DQS_NUMBER]; // 3 is channel number
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@ -6514,6 +6504,7 @@ U32 DramcRxWinRDDQCEnd(DRAMC_CTX_T *p)
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REG_TRANSFER_T TriggerReg = {DRAMC_REG_SWCMD_EN, SWCMD_EN_RDDQCEN};
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REG_TRANSFER_T RepondsReg = {DRAMC_REG_SPCMDRESP, SPCMDRESP_RDDQC_RESPONSE};
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u4Response = DramcTriggerAndWait(p, TriggerReg, RepondsReg);
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(void)u4Response;
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// Read RDDQC compare result
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u4TmpResult = u4IO32Read4B(DRAMC_REG_ADDR(DRAMC_REG_RDQC_CMP));
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@ -6538,14 +6529,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
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u8 isAutoK)
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{
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U8 u1BitIdx, u1ByteIdx;
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U16 u16DelayStep = 1;
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PASS_WIN_DATA_T FinalWinPerBit[DQ_DATA_WIDTH + RDDQC_ADD_DMI_NUM];
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S32 iDQSDlyPerbyte[DQS_NUMBER], iDQMDlyPerbyte[DQS_NUMBER];//, iFinalDQSDly[DQS_NUMBER];
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U8 u1VrefScanEnable = FALSE;
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U16 u2FinalVref [DQS_NUMBER]= {0xe, 0xe};
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U16 u2VrefBegin, u2VrefEnd, u2VrefStep;
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U8 u1RXEyeScanEnable=0,u1PrintCalibrationProc;
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U8 u1CalDQMNum = 0;
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U8 u1RXEyeScanEnable=0;
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#if ENABLE_EYESCAN_GRAPH
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U8 EyeScan_index[DQ_DATA_WIDTH_LP4 + RDDQC_ADD_DMI_NUM] = {0};
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@ -6580,14 +6569,12 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
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#if (FEATURE_RDDQC_K_DMI == TRUE)
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if (u1UseTestEngine == PATTERN_RDDQC)
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{
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u1CalDQMNum = 2;
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iDQMDlyPerbyte[0] = -0xFFFFFF;
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iDQMDlyPerbyte[1] = -0xFFFFFF;
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}
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else
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#endif
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{
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u1CalDQMNum = 0;
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iDQMDlyPerbyte[0] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B0_RXDLY4), SHU_R0_B0_RXDLY4_RX_ARDQM0_R_DLY_B0);
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iDQMDlyPerbyte[1] = u4IO32ReadFldAlign(DRAMC_REG_ADDR(DDRPHY_REG_SHU_R0_B1_RXDLY4), SHU_R0_B1_RXDLY4_RX_ARDQM0_R_DLY_B1);
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@ -6650,7 +6637,7 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
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u2VrefEnd = 0;
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u2VrefStep = 1;
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if ((u1UseTestEngine == PATTERN_TEST_ENGINE))
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if (u1UseTestEngine == PATTERN_TEST_ENGINE)
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{
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#if (FOR_DV_SIMULATION_USED==0 && SW_CHANGE_FOR_SIMULATION==0)
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if ((p->rank==RANK_0) || (p->frequency >= RX_VREF_DUAL_RANK_K_FREQ) || (u1RXEyeScanEnable==1))
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@ -6660,8 +6647,6 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
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#endif
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}
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u1PrintCalibrationProc = ((u1VrefScanEnable == 0) || (u1RXEyeScanEnable == 1) || (u1AssignedVref != NULL));
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#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
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if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
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{
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@ -6753,10 +6738,8 @@ DRAM_STATUS_T DramcRxWindowPerbitCal(DRAMC_CTX_T *p,
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u2VrefEnd = 0;
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u2VrefStep = 1;
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}
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(void)u2VrefStep;
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//if RDDQD, roughly calibration
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if (u1UseTestEngine == PATTERN_RDDQC)
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u16DelayStep <<= 1;
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#if SUPPORT_SAVE_TIME_FOR_CALIBRATION
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if (p->femmc_Ready == 1 && ((p->Bypass_RDDQC && u1UseTestEngine == PATTERN_RDDQC) || (p->Bypass_RXWINDOW && u1UseTestEngine == PATTERN_TEST_ENGINE)))
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@ -7270,9 +7253,7 @@ static void dle_factor_handler(DRAMC_CTX_T *p, U8 curr_val)
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static U8 aru1RxDatlatResult[RANK_MAX];
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DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
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{
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U32 u4prv_register_080;
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U8 ucfirst, ucbegin, ucsum, ucbest_step;
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U16 u2DatlatBegin;
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U8 ucbest_step;
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// error handling
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if (!p)
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@ -7286,7 +7267,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
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// pre-save
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// 0x07c[6:4] DATLAT bit2-bit0
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u4prv_register_080 = u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT));
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u4IO32Read4B(DRAMC_REG_ADDR(DDRPHY_REG_MISC_SHU_RDAT));
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//default set FAIL
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vSetCalibrationResult(p, DRAM_CALIBRATION_DATLAT, DRAM_FAIL);
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@ -7302,12 +7284,8 @@ DRAM_STATUS_T DramcRxdatlatCal(DRAMC_CTX_T *p)
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// 4.set DATLAT 2nd value for optimal
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// Initialize
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ucfirst = 0xff;
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ucbegin = 0;
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ucsum = 0;
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DramcEngine2Init(p, p->test2_1, p->test2_2, p->test_pattern | 0x80, 0, TE_UI_SHIFT);//UI_SHIFT + LEN1
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u2DatlatBegin = 0;
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#if (SUPPORT_SAVE_TIME_FOR_CALIBRATION && BYPASS_DATLAT)
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if (p->femmc_Ready == 1)
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@ -9352,9 +9330,6 @@ void DramcTxOECalibration(DRAMC_CTX_T *p)
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//U8 ucbegin=0xff, , ucfirst, ucsum, ucbest_step;
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U8 ucdq_oen_ui_large[2] = {0}, ucdq_oen_ui_small[2] = {0};
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//U8 ucdq_ui_large_reg_value=0xff, ucdq_ui_small_reg_value=0xff;
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U8 u1TxDQOEShift = 0;
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u1TxDQOEShift = TX_DQ_OE_SHIFT_LP4;
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#if TX_OE_PATTERN_USE_TA2
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msg("\n[DramC_TX_OE_Calibration] TA2\n");
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