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- Clean up and comment writing of MSRs for cache control (Backport from v3) 

- Invalidate Cache Tags (by means of in-place rewrite of cache data) which allows CAR data to be flushed to RAM
- Re-enable cache after flush of CAR to RAM


Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Edwin Beasant 2010-01-26 11:22:43 +00:00 committed by Patrick Georgi
parent e8d943f266
commit a9796ed362
2 changed files with 48 additions and 52 deletions
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40
src/cpu/amd/model_lx/cache_as_ram.inc
View File

@ -178,31 +178,28 @@ DCacheSetupGood:
call cache_as_ram_main
done_cache_as_ram_main:
/* If you wanted to maintain the stack in memory you would need to set the tags as dirty
so the wbinvd would push out the old stack contents to memory */
/* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
push %edi
mov $(CONFIG_DCACHE_RAM_SIZE/4),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi
cld
rep movsl %ds:(%esi),%es:(%edi)
pop %esi
pop %edi
/* Clear the cache out to ram */
wbinvd
/* the following code is from crt0.S.lb */
/* This takes the place of the post-CAR funtions that the K8 uses to setup the stack and copy LB low.*/
#ifndef CONSOLE_DEBUG_TX_STRING
/* uses: esp, ebx, ax, dx */
# define __CRT_CONSOLE_TX_STRING(string) \
mov string, %ebx ; \
CALLSP(crt_console_tx_string)
# if defined(CONFIG_TTYS0_BASE) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG)
# define CONSOLE_DEBUG_TX_STRING(string) __CRT_CONSOLE_TX_STRING(string)
# else
# define CONSOLE_DEBUG_TX_STRING(string)
# endif
#endif
/* re-enable the cache */
movl %cr0, %eax
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0
/* clear boot_complete flag */
xorl %ebp, %ebp
__main:
CONSOLE_DEBUG_TX_STRING($str_copying_to_ram)
/*
* Copy data into RAM and clear the BSS. Since these segments
@ -218,9 +215,6 @@ __main:
* Normally this is copying from FLASH ROM to RAM.
*/
movl %ebp, %esi
/* FIXME: look for a proper place for the stack */
movl $0x4000000, %esp
movl %esp, %ebp
pushl %esi
pushl $str_coreboot_ram_name
call cbfs_and_run_core

60
src/mainboard/amd/db800/cache_as_ram_auto.c
View File

@ -35,6 +35,7 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@ -60,37 +61,38 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#include "cpu/amd/model_lx/cpureginit.c"
#include "cpu/amd/model_lx/syspreinit.c"
struct msrinit {
u32 msrnum;
msr_t msr;
};
static const struct msrinit msr_table[] =
{
{CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
* Rom Properties: Write Serialize, WriteProtect.
* RomBase: 0xFFFC0
* SysTop to RomBase Properties: Write Serialize, Cache Disable.
* SysTop: 0x000A0
* System Memory Properties: (Write Back) */
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xC0000-0xDFFFF : (Write Back) */
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xE0000-0xFFFFF : (Write Back) */
/* Setup access to memory under 1MB. Note: VGA hole at 0xA0000-0xBFFFF */
{MSR_GLIU0_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
{MSR_GLIU0_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
{MSR_GLIU0_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
{MSR_GLIU1_BASE1, {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
{MSR_GLIU1_BASE2, {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
{MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
};
static void msr_init(void)
{
msr_t msr;
/* Setup access to the cache for under 1MB. */
msr.hi = 0x24fffc02;
msr.lo = 0x1000A000; /* 0-A0000 write back */
wrmsr(CPU_RCONF_DEFAULT, msr);
msr.hi = 0x0; /* Write back */
msr.lo = 0x0;
wrmsr(CPU_RCONF_A0_BF, msr);
wrmsr(CPU_RCONF_C0_DF, msr);
wrmsr(CPU_RCONF_E0_FF, msr);
/* Setup access to the cache for under 640K. Note MC not setup yet. */
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU0 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU0 + 0x21, msr);
msr.hi = 0x20000000;
msr.lo = 0xfff80;
wrmsr(MSR_GLIU1 + 0x20, msr);
msr.hi = 0x20000000;
msr.lo = 0x80fffe0;
wrmsr(MSR_GLIU1 + 0x21, msr);
int i;
for (i = 0; i < ARRAY_SIZE(msr_table); i++)
wrmsr(msr_table[i].msrnum, msr_table[i].msr);
}
static void mb_gpio_init(void)