rk3288: support tsadc

check the cpu and gpu temperature in romstage,
if over 120 degrees celsius,shut down the device.

BUG=None
Test=Boot on veyron_pinky rev2, write value
3421(125 celsius) to grf_tsadc_testbitl register,
the device will be shut down

Change-Id: I275d643ce8560444a9b42ee566d5fd63ebcda35e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e0c597489dc0637ffa66ee9db0c4f60757f8889f
Original-Change-Id: If406d6a4f6201150f52ea7fc64cd50b45778d7aa
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/223259
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9348
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/veyron_pinky/romstage.c

@@ -35,6 +35,7 @@
 #include <soc/rockchip/rk3288/clock.h>
 #include <soc/rockchip/rk3288/pwm.h>
 #include <soc/rockchip/rk3288/grf.h>
+#include <soc/rockchip/rk3288/tsadc.h>
 #include <symbols.h>
 #include "timer.h"
 
@@ -86,6 +87,7 @@ void main(void)
 
 	console_init();
 	configure_l2ctlr();
+	tsadc_init();
 
 	/* vdd_log 1200mv is enough for ddr run 666Mhz */
 	regulate_vdd_log(1200);

src/soc/rockchip/rk3288/Makefile.inc

@@ -53,6 +53,7 @@ romstage-y += spi.c
 romstage-y += media.c
 romstage-y += sdram.c
 romstage-y += pwm.c
+romstage-y += tsadc.c
 
 ramstage-y += soc.c
 ramstage-y += cbmem.c

src/soc/rockchip/rk3288/addressmap.h

@@ -36,6 +36,7 @@
 #define UART0_BASE		0xFF180000
 #define UART1_BASE		0xFF190000
 #define DMAC_PERI_BASE		0xFF250000
+#define TSADC_BASE		0xFF280000
 
 #define NANDC0_BASE		0xFF400000
 #define NANDC1_BASE		0xFF410000

src/soc/rockchip/rk3288/clock.c

@@ -480,3 +480,14 @@ void rkclk_configure_i2s(unsigned int hz)
 	assert(hz == GPLL_HZ / n * d);
 	writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]);
 }
+
+void rkclk_configure_tsadc(unsigned int hz)
+{
+	u32 div;
+	u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/
+
+	div = src_clk / hz;
+	assert((div - 1 < 64) && (div * hz == 32 * KHz));
+	writel(RK_CLRSETBITS(0x3f << 0, (div - 1) << 0),
+			&cru_ptr->cru_clksel_con[2]);
+}

src/soc/rockchip/rk3288/clock.h

@@ -43,4 +43,6 @@ void rkclk_ddr_phy_ctl_reset(u32 ch, u32 n);
 void rkclk_configure_ddr(unsigned int hz);
 void rkclk_configure_i2s(unsigned int hz);
 void rkclk_configure_cpu(void);
+void rkclk_configure_tsadc(unsigned int hz);
+
 #endif	/* __SOC_ROCKCHIP_RK3288_CLOCK_H__ */

src/soc/rockchip/rk3288/pmu.h

@@ -54,6 +54,7 @@ struct rk3288_pmu_regs {
 	union {
 		u32 gpio0b_iomux;
 		u32 iomux_i2c0sda;
+		u32 iomux_tsadc_int;
 	};
 	union {
 		u32 gpio0c_iomux;
@@ -69,7 +70,8 @@ check_member(rk3288_pmu_regs, sys_reg[3], 0x00a0);
 
 static struct rk3288_pmu_regs * const rk3288_pmu = (void *)PMU_BASE;
 
-#define IOMUX_I2C0SDA	1 << 14
-#define IOMUX_I2C0SCL	1 << 0
+#define IOMUX_I2C0SDA	(1 << 14)
+#define IOMUX_I2C0SCL	(1 << 0)
+#define	IOMUX_TSADC_INT	(1 << 4)
 
 #endif

src/soc/rockchip/rk3288/tsadc.c

@@ -0,0 +1,119 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <assert.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "tsadc.h"
+#include "clock.h"
+#include "pmu.h"
+#include "grf.h"
+
+struct rk3288_tsadc_regs {
+	u32	user_con;
+	u32	auto_con;
+	u32	int_en;
+	u32	int_pd;
+	u32	reserved0[(0x20 - 0x10) / 4];
+	u32	data0;
+	u32	data1;
+	u32	data2;
+	u32	data3;
+	u32	comp0_int;
+	u32	comp1_int;
+	u32	comp2_int;
+	u32	comp3_int;
+	u32	comp0_shut;
+	u32	comp1_shut;
+	u32	comp2_shut;
+	u32	comp3_shut;
+	u32	reserved1[(0x60 - 0x50) / 4];
+	u32	hight_int_debounce;
+	u32	hight_tshut_debounce;
+	u32	auto_period;
+	u32	auto_period_ht;
+};
+check_member(rk3288_tsadc_regs, auto_period_ht, 0x6c);
+
+/* auto_con */
+#define LAST_TSHUT	(1 << 24)
+#define TSHUT_POL_HIGH	(1 << 8)
+#define SRC3_EN		(1 << 7)
+#define SRC2_EN		(1 << 6)
+#define SRC1_EN		(1 << 5)
+#define SRC0_EN		(1 << 4)
+#define AUTO_EN		(1 << 0)
+
+/* int_en */
+#define TSHUT_CRU_EN_SRC3	(1 << 11)
+#define TSHUT_CRU_EN_SRC2	(1 << 10)
+#define TSHUT_CRU_EN_SRC1	(1 << 9)
+#define TSHUT_CRU_EN_SRC0	(1 << 8)
+#define TSHUT_GPIO_EN_SRC3	(1 << 7)
+#define TSHUT_GPIO_EN_SRC2	(1 << 6)
+#define TSHUT_GPIO_EN_SRC1	(1 << 5)
+#define TSHUT_GPIO_EN_SRC0	(1 << 4)
+
+#define AUTO_PERIOD	10
+#define AUTO_DEBOUNCE	4
+#define AUTO_PERIOD_HT	10
+#define AUTO_DEBOUNCE_HT	4
+#define TSADC_CLOCK_HZ		(8 * KHz)
+
+/* AD value, correspond to 120 degrees Celsius */
+#define TSADC_SHUT_VALUE	3437
+
+struct rk3288_tsadc_regs *rk3288_tsadc = (void *)TSADC_BASE;
+
+void tsadc_init(void)
+{
+	rkclk_configure_tsadc(TSADC_CLOCK_HZ);
+
+	if (readl(&rk3288_tsadc->auto_con) & LAST_TSHUT) {
+		printk(BIOS_WARNING, "last shutdown/rebot was caused "
+				"by over-temperature hardware trigger!\n");
+		setbits_le32(&rk3288_tsadc->auto_con, LAST_TSHUT);
+	}
+
+	setbits_le32(&rk3288_tsadc->int_en,
+			TSHUT_CRU_EN_SRC2 | TSHUT_CRU_EN_SRC1 |
+			TSHUT_GPIO_EN_SRC2 | TSHUT_GPIO_EN_SRC1);
+
+	writel(AUTO_PERIOD, &rk3288_tsadc->auto_period);
+	writel(AUTO_DEBOUNCE, &rk3288_tsadc->hight_int_debounce);
+	writel(AUTO_PERIOD_HT, &rk3288_tsadc->auto_period_ht);
+	writel(AUTO_DEBOUNCE_HT, &rk3288_tsadc->hight_tshut_debounce);
+
+	writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp1_shut);
+	writel(TSADC_SHUT_VALUE, &rk3288_tsadc->comp2_shut);
+
+	/* polarity set to high,channel1 for cpu,channel2 for gpu */
+	setbits_le32(&rk3288_tsadc->auto_con, TSHUT_POL_HIGH | SRC2_EN |
+				SRC1_EN | AUTO_EN);
+
+	/*
+	  tsadc iomux must be set after the tshut polarity setting,
+	  since the tshut polarity defalut low active,
+	  so if you enable tsadc iomux,it will output high
+	 */
+	setbits_le32(&rk3288_pmu->iomux_tsadc_int, IOMUX_TSADC_INT);
+}

src/soc/rockchip/rk3288/tsadc.h

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_TSADC_H__
+#define __SOC_ROCKCHIP_RK3288_TSADC_H__
+
+void tsadc_init(void);
+
+#endif