cpu/amd/car: Increase Family 10h CAR size limit to 128k
This resolves issues with 4-node (32-core) systems not having sufficient CAR memory available to boot. TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores) and 120k of CAR. Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/10402 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -3,6 +3,7 @@
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*
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*
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* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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* Copyright (C) 2008 Carl-Daniel Hailfinger
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -250,9 +251,15 @@ clear_fixed_var_mtrr_out:
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*/
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*/
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.endm
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.endm
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#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
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#if CacheSize > 0x80000
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#error Invalid CAR size, must be at most 128k (processor limit is 512k).
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#endif
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#else
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#if CacheSize > 0x10000
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#if CacheSize > 0x10000
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#error Invalid CAR size, must be at most 64k.
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#error Invalid CAR size, must be at most 64k.
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#endif
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#endif
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#endif
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#if CacheSize < 0x1000
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#if CacheSize < 0x1000
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#error Invalid CAR size, must be at least 4k. This is a processor limitation.
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#endif
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#endif
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@ -267,6 +274,20 @@ clear_fixed_var_mtrr_out:
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wrmsr
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wrmsr
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#endif
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#endif
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#if CacheSize > 0x10000
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/* Enable caching for 64K-96K using fixed MTRR. */
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movl $MTRRfix4K_D0000_MSR, %ecx
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simplemask CacheSize, 0x10000
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wrmsr
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#endif
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#if CacheSize > 0x18000
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/* Enable caching for 96K-128K using fixed MTRR. */
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movl $MTRRfix4K_D8000_MSR, %ecx
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simplemask CacheSize, 0x18000
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wrmsr
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#endif
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/* Enable caching for 0-32K using fixed MTRR. */
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/* Enable caching for 0-32K using fixed MTRR. */
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movl $MTRRfix4K_C8000_MSR, %ecx
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movl $MTRRfix4K_C8000_MSR, %ecx
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simplemask CacheSize, 0
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simplemask CacheSize, 0
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@ -4,6 +4,7 @@
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* original idea yhlu 6.2005 (assembler code)
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* original idea yhlu 6.2005 (assembler code)
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*
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*
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* Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -35,6 +36,12 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
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wrmsr(MTRRfix4K_C8000_MSR, msr);
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wrmsr(MTRRfix4K_C8000_MSR, msr);
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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#if CONFIG_DCACHE_RAM_SIZE > 0x8000
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wrmsr(MTRRfix4K_C0000_MSR, msr);
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wrmsr(MTRRfix4K_C0000_MSR, msr);
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#endif
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#if CONFIG_DCACHE_RAM_SIZE > 0x10000
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wrmsr(MTRRfix4K_D0000_MSR, msr);
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#endif
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#if CONFIG_DCACHE_RAM_SIZE > 0x18000
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wrmsr(MTRRfix4K_D8000_MSR, msr);
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#endif
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#endif
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/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
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/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
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