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cpu/amd/car: Increase Family 10h CAR size limit to 128k 

This resolves issues with 4-node (32-core) systems not having
sufficient CAR memory available to boot.

TEST: Booted ASUS KGPE-D16 with dual Opteron 6129 processors (16 cores)
and 120k of CAR.

Change-Id: Ie884556edc5c85c2c908a8c6640eeec11594ba3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10402
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Timothy Pearson 2015-06-02 13:53:25 -05:00 committed by Stefan Reinauer
parent b5e465522e
commit a97e0075a2
2 changed files with 30 additions and 2 deletions
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25
src/cpu/amd/car/cache_as_ram.inc
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2005-2007 Advanced Micro Devices, Inc.
* Copyright (C) 2008 Carl-Daniel Hailfinger
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -250,8 +251,14 @@ clear_fixed_var_mtrr_out:
*/
.endm
#if CacheSize > 0x10000
#error Invalid CAR size, must be at most 64k.
#if IS_ENABLED(CONFIG_CPU_AMD_MODEL_10XXX)
#if CacheSize > 0x80000
#error Invalid CAR size, must be at most 128k (processor limit is 512k).
#endif
#else
#if CacheSize > 0x10000
#error Invalid CAR size, must be at most 64k.
#endif
#endif
#if CacheSize < 0x1000
#error Invalid CAR size, must be at least 4k. This is a processor limitation.
@ -267,6 +274,20 @@ clear_fixed_var_mtrr_out:
wrmsr
#endif
#if CacheSize > 0x10000
/* Enable caching for 64K-96K using fixed MTRR. */
movl $MTRRfix4K_D0000_MSR, %ecx
simplemask CacheSize, 0x10000
wrmsr
#endif
#if CacheSize > 0x18000
/* Enable caching for 96K-128K using fixed MTRR. */
movl $MTRRfix4K_D8000_MSR, %ecx
simplemask CacheSize, 0x18000
wrmsr
#endif
/* Enable caching for 0-32K using fixed MTRR. */
movl $MTRRfix4K_C8000_MSR, %ecx
simplemask CacheSize, 0

7
src/cpu/amd/car/disable_cache_as_ram.c
View File

@ -4,6 +4,7 @@
* original idea yhlu 6.2005 (assembler code)
*
* Copyright (C) 2010 Rudolf Marek <r.marek@assembler.cz>
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -35,6 +36,12 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
wrmsr(MTRRfix4K_C8000_MSR, msr);
#if CONFIG_DCACHE_RAM_SIZE > 0x8000
wrmsr(MTRRfix4K_C0000_MSR, msr);
#endif
#if CONFIG_DCACHE_RAM_SIZE > 0x10000
wrmsr(MTRRfix4K_D0000_MSR, msr);
#endif
#if CONFIG_DCACHE_RAM_SIZE > 0x18000
wrmsr(MTRRfix4K_D8000_MSR, msr);
#endif
/* disable fixed mtrr from now on, it will be enabled by ramstage again*/