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southbridge/amd/sr5650/sr5650.c: Fix bitwise logic and mask in loop 

Correct mask to select bits 4-6 inclusively as per comment and use
bitwise operations while working with bits. Be sure to write back out
the data on the retrain.

See:
 commit cab9efb2 southbridge/amd/rsXY0/cmn.c: Fix bitwise logic and mask in loop

Change-Id: I95d1799514157b7849f3e473837aaf2fd9bd59b9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7692
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Edward O'Callaghan 2014-12-08 03:00:26 +11:00
parent b3b79afd55
commit a9a2e10eed
1 changed files with 3 additions and 4 deletions
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src/southbridge/amd/sr5650/sr5650.c
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@ -238,13 +238,12 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port)
if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */
/* set bit8=1, bit0-2=bit4-6 */ /* set bit8=1, bit0-2=bit4-6 */
u32 tmp; u32 tmp;
reg = reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH);
nbpcie_p_read_index(dev, tmp = (reg >> 4) & 0x7; /* get bit4-6 */
PCIE_LC_LINK_WIDTH);
tmp = (reg >> 4) && 0x3; /* get bit4-6 */
reg &= 0xfff8; /* clear bit0-2 */ reg &= 0xfff8; /* clear bit0-2 */
reg += tmp; /* merge */ reg += tmp; /* merge */
reg |= 1 << 8; reg |= 1 << 8;
nbpcie_p_write_index(dev, PCIE_LC_LINK_WIDTH, reg);
count++; /* CIM said "keep in loop"? */ count++; /* CIM said "keep in loop"? */
} else { } else {
res = 1; res = 1;