mb/intel/adlrvp: Add PMC.MUX.CONx device configuration for adlrvp

This patch adds the PMC MUX and CONx devices for adlrvp. Device
specific method contains the port and orientation details used
to configure the mux.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.

Change-Id: I3b5bb73991feb99577c16fea00c381dd0f855769
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

src/mainboard/intel/adlrvp/Kconfig

@@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select DRIVERS_I2C_HID
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_INTEL_SOUNDWIRE
+	select DRIVERS_INTEL_PMC if BOARD_INTEL_ADLRVP_P_EXT_EC
 	select DRIVERS_USB_ACPI
 	select DRIVERS_SPI_ACPI
 	select SOC_INTEL_ALDERLAKE

src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb

@@ -1,4 +1,34 @@
 chip soc/intel/alderlake
 
-	device domain 0 on end
+	device domain 0 on
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+				use conn0 as mux_conn[0]
+				use conn1 as mux_conn[1]
+			end
+		end # eSPI
+		device pci 1f.2 hidden
+			# The pmc_mux chip driver is a placeholder for the
+			# PMC.MUX device in the ACPI hierarchy.
+			chip drivers/intel/pmc_mux
+				device generic 0 on
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "1"
+						register "usb3_port_number" = "1"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 0 alias conn0 on end
+					end
+					chip drivers/intel/pmc_mux/conn
+						register "usb2_port_number" = "2"
+						register "usb3_port_number" = "2"
+						# SBU is fixed, HSL follows CC
+						register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
+						device generic 1 alias conn1 on end
+					end
+				end
+			end
+		end # PMC
+	end
 end