From a9b01d13476eae77b4a1f1679b29eced69684492 Mon Sep 17 00:00:00 2001
From: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Date: Wed, 21 Aug 2013 10:06:25 +0800
Subject: [PATCH] AMD f16kb: use AZ_PIN in Kconfig to customize AZALIA_PIN in
 Yangtze

src/southbridge/amd/agesa/hudson/Kconfig config default value,
mainboard Kconfig config value for specific mainboard.
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3

Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3879
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
---
 src/southbridge/amd/agesa/hudson/Kconfig                 | 9 +++++++++
 .../Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c    | 8 ++++----
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index 5cb17223f7..7e7399c090 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -247,4 +247,13 @@ if SOUTHBRIDGE_AMD_AGESA_YANGTZE
 	config AMD_SB_SPI_TX_LEN
 		int
 		default 64
+
+	config AZ_PIN
+		hex
+		default 0xaa
+		help
+		  bit 1,0 - pin 0
+		  bit 3,2 - pin 1
+		  bit 5,4 - pin 2
+		  bit 7,6 - pin 3
 endif
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
index 888b83c186..f638e715dd 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c
@@ -266,10 +266,10 @@ FCH_DATA_BLOCK   InitEnvCfgDefault = {
     0,                       // AzaliaSnoop
     0,                       // AzaliaDummy
     {                        // AZALIA_PIN
-      2,                     // AzaliaSdin0
-      2,                     // AzaliaSdin1
-      2,                     // AzaliaSdin2
-      2,                     // AzaliaSdin3
+      CONFIG_AZ_PIN & 0x3,                     // AzaliaSdin0
+      (CONFIG_AZ_PIN & 0xc) >> 2,              // AzaliaSdin1
+      (CONFIG_AZ_PIN & 0x30) >> 4,             // AzaliaSdin2
+      (CONFIG_AZ_PIN & 0xc0) >> 6,             // AzaliaSdin3
     },
     NULL,                    // *AzaliaOemCodecTablePtr
     NULL,                    // *AzaliaOemFpCodecTablePtr