google/glados: Enable TPM PIRQ
Enable the config option for TPM to use PIRQ instead of SERIRQ and enable the MAINBOARD_HAS_LPC_TPM option. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I990901117a2c478045c403f1039d6eedfc278255 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44ecaaae1eb482ef5d4cf1e051de4571cc4441be Original-Change-Id: I115d468c72c3fd015abdddffdd1626368bfedb6e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304925 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_OPTION_TABLE
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select HAVE_OPTION_TABLE
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select HAVE_SMI_HANDLER
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select HAVE_SMI_HANDLER
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_LPC_TPM
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select MARK_GRAPHICS_MEM_WRCOMB
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select MARK_GRAPHICS_MEM_WRCOMB
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT
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select MONOTONIC_TIMER_MSR
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select MONOTONIC_TIMER_MSR
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@ -48,6 +49,10 @@ config MAX_CPUS
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int
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int
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default 8
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default 8
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config TPM_PIRQ
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hex
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default 0x18 # GPP_E0_IRQ
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config VBOOT_RAMSTAGE_INDEX
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config VBOOT_RAMSTAGE_INDEX
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hex
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hex
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default 0x3
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default 0x3
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