sb/common/intel/spi.c: Don't use typedefs for structs
Change-Id: Id0ed621b5b4b5634d454811b1e1beeb27fc69ea8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Arthur Heymans
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b0bbafe5ad
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a9c1a5f1f8
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@ -38,11 +38,9 @@
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static int spi_is_multichip(void);
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typedef struct spi_slave ich_spi_slave;
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static int g_ichspi_lock = 0;
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typedef struct ich7_spi_regs {
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struct ich7_spi_regs {
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uint16_t spis;
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uint16_t spic;
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uint32_t spia;
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@ -53,9 +51,9 @@ typedef struct ich7_spi_regs {
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uint16_t optype;
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uint8_t opmenu[8];
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uint32_t pbr[3];
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} __packed ich7_spi_regs;
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} __packed;
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typedef struct ich9_spi_regs {
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struct ich9_spi_regs {
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uint32_t bfpr;
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uint16_t hsfs;
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uint16_t hsfc;
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@ -86,15 +84,15 @@ typedef struct ich9_spi_regs {
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uint32_t srdl;
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uint32_t srdc;
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uint32_t srd;
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} __packed ich9_spi_regs;
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} __packed;
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typedef struct ich_spi_controller {
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struct ich_spi_controller {
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int locked;
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uint32_t flmap0;
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uint32_t flcomp;
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uint32_t hsfs;
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ich9_spi_regs *ich9_spi;
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struct ich9_spi_regs *ich9_spi;
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uint8_t *opmenu;
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int menubytes;
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uint16_t *preop;
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@ -107,9 +105,9 @@ typedef struct ich_spi_controller {
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uint32_t *bbar;
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uint32_t *fpr;
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uint8_t fpr_max;
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} ich_spi_controller;
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};
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static ich_spi_controller g_cntlr;
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static struct ich_spi_controller g_cntlr;
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enum {
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SPIS_SCIP = 0x0001,
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@ -254,7 +252,7 @@ static void read_reg(const void *src, void *value, uint32_t size)
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static void ich_set_bbar(uint32_t minaddr)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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@ -266,12 +264,12 @@ static void ich_set_bbar(uint32_t minaddr)
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void spi_init(void)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint8_t *rcrb; /* Root Complex Register Block */
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uint32_t rcba; /* Root Complex Base Address */
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uint8_t bios_cntl;
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ich9_spi_regs *ich9_spi;
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ich7_spi_regs *ich7_spi;
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struct ich9_spi_regs *ich9_spi;
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struct ich7_spi_regs *ich7_spi;
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uint16_t hsfs;
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#ifdef __SIMPLE_DEVICE__
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@ -284,7 +282,7 @@ void spi_init(void)
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/* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */
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rcrb = (uint8_t *)(rcba & 0xffffc000);
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
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ich7_spi = (ich7_spi_regs *)(rcrb + 0x3020);
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ich7_spi = (struct ich7_spi_regs *)(rcrb + 0x3020);
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cntlr->opmenu = ich7_spi->opmenu;
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cntlr->menubytes = sizeof(ich7_spi->opmenu);
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cntlr->optype = &ich7_spi->optype;
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@ -299,7 +297,7 @@ void spi_init(void)
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cntlr->fpr = &ich7_spi->pbr[0];
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cntlr->fpr_max = 3;
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} else {
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ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
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ich9_spi = (struct ich9_spi_regs *)(rcrb + 0x3800);
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cntlr->ich9_spi = ich9_spi;
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hsfs = readw_(&ich9_spi->hsfs);
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g_ichspi_lock = hsfs & HSFS_FLOCKDN;
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@ -399,7 +397,7 @@ static void spi_setup_type(spi_transaction *trans)
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static int spi_setup_opcode(spi_transaction *trans)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint16_t optypes;
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uint8_t opmenu[cntlr->menubytes];
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@ -480,7 +478,7 @@ static int spi_setup_offset(spi_transaction *trans)
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*/
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static int ich_status_poll(u16 bitmask, int wait_til_set)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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int timeout = 600000; /* This will result in 6 seconds */
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u16 status = 0;
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@ -501,7 +499,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
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static int spi_is_multichip(void)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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if (!(cntlr->hsfs & HSFS_FDV))
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return 0;
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return !!((cntlr->flmap0 >> 8) & 3);
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@ -510,7 +508,7 @@ static int spi_is_multichip(void)
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static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
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size_t bytesout, void *din, size_t bytesin)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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@ -660,7 +658,7 @@ spi_xfer_exit:
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/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
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static void ich_hwseq_set_addr(uint32_t addr)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
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writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
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@ -673,7 +671,7 @@ static void ich_hwseq_set_addr(uint32_t addr)
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static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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unsigned int len)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint16_t hsfs;
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uint32_t addr;
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@ -713,7 +711,7 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
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static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
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size_t len)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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u32 start, end, erase_size;
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int ret;
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uint16_t hsfc;
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@ -763,7 +761,7 @@ out:
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static void ich_read_data(uint8_t *data, int len)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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int i;
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uint32_t temp32 = 0;
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@ -778,7 +776,7 @@ static void ich_read_data(uint8_t *data, int len)
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static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
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void *buf)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint16_t hsfc;
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uint16_t timeout = 100 * 60;
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uint8_t block_len;
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@ -824,7 +822,7 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
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*/
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static void ich_fill_data(const uint8_t *data, int len)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint32_t temp32 = 0;
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int i;
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@ -848,7 +846,7 @@ static void ich_fill_data(const uint8_t *data, int len)
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static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
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const void *buf)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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uint16_t hsfc;
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uint16_t timeout = 100 * 60;
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uint8_t block_len;
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@ -904,7 +902,7 @@ static const struct spi_flash_ops spi_flash_ops = {
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static int spi_flash_programmer_probe(const struct spi_slave *spi,
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struct spi_flash *flash)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX))
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return spi_flash_generic_probe(spi, flash);
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@ -984,7 +982,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
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const struct region *region,
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const enum ctrlr_prot_type type)
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{
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ich_spi_controller *cntlr = &g_cntlr;
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struct ich_spi_controller *cntlr = &g_cntlr;
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u32 start = region_offset(region);
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u32 end = start + region_sz(region) - 1;
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u32 reg;
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@ -1043,7 +1041,7 @@ static int spi_flash_protect(const struct spi_flash *flash,
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static const struct spi_ctrlr spi_ctrlr = {
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.xfer_vector = xfer_vectors,
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.max_xfer_size = member_size(ich9_spi_regs, fdata),
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.max_xfer_size = member_size(struct ich9_spi_regs, fdata),
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.flash_probe = spi_flash_programmer_probe,
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.flash_protect = spi_flash_protect,
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};
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