From a9cd4a2f117f03abb4e4433b040c2225242fd35f Mon Sep 17 00:00:00 2001 From: Vadim Bendebury Date: Thu, 12 May 2016 16:40:37 +0800 Subject: [PATCH] rk3399: add GPIO register definitions for SDMMC0 The code needs to be able to set drive strength for the pins used for SDMMC0 interface. This patch adds the definitions for the two registers, as per page 378 of the RK3399 TRM Part 1. Instead of calculation of the reserved range size just use known offsets of the registers included in the structure. BRANCH=none BUG=chrome-os-partner:53257 TEST=with the upcoming driver change it is possible to boot chrome OS on Gru from various micro SD cards which were failing before. Change-Id: I63bf37432ec7f3bdf7e9c6a79d51c31de122dae9 Signed-off-by: Martin Roth Original-Commit-Id: c6d6dc5e5e6cc81c173603d4eb21ae803a47815d Original-Change-Id: Ibe7584e77b446435ab1264dcf8fc8bfe0c50438e Original-Signed-off-by: Vadim Bendebury Original-Reviewed-on: https://chromium-review.googlesource.com/344490 Original-Reviewed-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/14852 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury --- src/soc/rockchip/rk3399/include/soc/grf.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index 389454f0c7..df1fb031c8 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -149,7 +149,10 @@ struct rk3399_grf_regs { u32 gpio2_sr[3][4]; u32 reserved23[4]; u32 gpio2_smt[3][4]; - u32 reserved24[0x44]; + u32 reserved24[(0xe130 - 0xe0ec)/4 - 1]; + u32 gpio4b_e01; + u32 gpio4b_e2; + u32 reserved24a[(0xe200 - 0xe134)/4 - 1]; u32 soc_con0; u32 soc_con1; u32 soc_con2;