mb/google/hatch: Add NC gpios for display and correct the order
Correcting order of display related GPIOs and also adding not connected pin definitions for display GPIOs BUG=b:120914069 BRANCH=none TEST=check if code compiles with changes. Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/30544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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@ -55,6 +55,22 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
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/* USB_A_OC_OD USB_OC3*/
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
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/* USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD_ODL */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* DDPD_HPD2 => NC */
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PAD_NC(GPP_E15, DN_20K),
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/* DDPE_HPD2 => NC */
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PAD_NC(GPP_E16, DN_20K),
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/* EDP_HPD */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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/* DDPB_CTRLCLK => NC */
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PAD_NC(GPP_E18, DN_20K),
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/* DDPC_CTRLCLK => NC */
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PAD_NC(GPP_E20, DN_20K),
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/* DDPD_CTRLCLK => NC */
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PAD_NC(GPP_E22, DN_20K),
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/* PCH_MEM_STRAP0 */
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PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
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/* PCH_MEM_STRAP1 */
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@ -63,12 +79,6 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
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/* PCH_MEM_STRAP3 */
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PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
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/* USB_C0_DP_HPD */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
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/* DDI2_HPD_ODL */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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/* EDP_HPD */
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
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};
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const struct pad_config *__weak variant_gpio_table(size_t *num)
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