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mb/google/hatch: Add NC gpios for display and correct the order 

Correcting order of display related GPIOs and also adding not connected
pin definitions for display GPIOs

BUG=b:120914069
BRANCH=none
TEST=check if code compiles with changes.

Change-Id: I9498284d263516f65513d6395883b6b09dd70fd5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/30544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This commit is contained in:
Maulik V Vaghela 2018-12-31 09:57:48 +05:30 committed by Subrata Banik
parent 2e658f8edf
commit a9fadb007d
1 changed files with 16 additions and 6 deletions
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22
src/mainboard/google/hatch/variants/baseboard/gpio.c
View File

@ -55,6 +55,22 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB_A_OC_OD USB_OC3*/
PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* USB_C0_DP_HPD */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDI2_HPD_ODL */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* DDPD_HPD2 => NC */
PAD_NC(GPP_E15, DN_20K),
/* DDPE_HPD2 => NC */
PAD_NC(GPP_E16, DN_20K),
/* EDP_HPD */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK => NC */
PAD_NC(GPP_E18, DN_20K),
/* DDPC_CTRLCLK => NC */
PAD_NC(GPP_E20, DN_20K),
/* DDPD_CTRLCLK => NC */
PAD_NC(GPP_E22, DN_20K),
/* PCH_MEM_STRAP0 */
PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
/* PCH_MEM_STRAP1 */
@ -63,12 +79,6 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
/* PCH_MEM_STRAP3 */
PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
/* USB_C0_DP_HPD */
PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDI2_HPD_ODL */
PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* EDP_HPD */
PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
};
const struct pad_config *__weak variant_gpio_table(size_t *num)