This patch implements support for the Intel 3100 integrated
northbridge and RAM controller. Signed-off-by: Ed Swierk <eswierk@arastra.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ed Swierk
Stefan Reinauer
parent
aaea11b749
commit
a9faea8977
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2008 Arastra, Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License version 2 as
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||||
## published by the Free Software Foundation.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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||||
## along with this program; if not, write to the Free Software
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||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config chip.h
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driver northbridge.o
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driver pciexp_porta.o
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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||||
*
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* This program is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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struct northbridge_intel_i3100_config
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{
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/* Interrupt line connect */
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u16 intrline;
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};
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extern struct chip_operations northbridge_intel_i3100_ops;
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@ -0,0 +1,59 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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||||
* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#define IURBASE 0X14
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#define MCHCFG0 0X50
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#define MCHSCRB 0X52
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#define FDHC 0X58
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#define PAM 0X59
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#define DRB 0X60
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#define DRA 0X70
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#define DRT 0X78
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#define DRC 0X7C
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#define DRM 0X80
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#define DRORC 0X82
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#define ECCDIAG 0X84
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#define SDRC 0X88
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#define CKDIS 0X8C
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#define CKEDIS 0X8D
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#define DDRCSR 0X9A
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#define DEVPRES 0X9C
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#define DEVPRES_D0F0 (1 << 0)
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#define DEVPRES_D1F0 (1 << 1)
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#define DEVPRES_D2F0 (1 << 2)
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#define DEVPRES_D3F0 (1 << 3)
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#define DEVPRES_D4F0 (1 << 4)
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#define DEVPRES_D5F0 (1 << 5)
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#define DEVPRES_D6F0 (1 << 6)
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#define DEVPRES_D7F0 (1 << 7)
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#define ESMRC 0X9D
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#define SMRC 0X9E
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#define EXSMRC 0X9F
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#define DDR2ODTC 0XB0
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#define TOLM 0XC4
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#define REMAPBASE 0XC6
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#define REMAPLIMIT 0XC8
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#define REMAPOFFSET 0XCA
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#define TOM 0XCC
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#define EXPECBASE 0XCE
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#define DEVPRES1 0XF4
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#define DEVPRES1_D0F1 (1 << 5)
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#define DEVPRES1_D8F0 (1 << 1)
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#define MSCFG 0XF6
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@ -0,0 +1,29 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#include "i3100.h"
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#define NB_DEV PCI_DEV(0, 0, 0)
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static inline int memory_initialized(void)
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{
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u32 drc;
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drc = pci_read_config32(NB_DEV, DRC);
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return (drc & (1<<29));
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}
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@ -0,0 +1,291 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Arastra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
|
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* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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/* This code is based on src/northbridge/intel/e7520/northbridge.c */
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/hypertransport.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include <cpu/cpu.h>
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#include "chip.h"
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#include "i3100.h"
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static u32 max_bus;
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static void ram_resource(device_t dev, u32 index,
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u32 basek, u32 sizek)
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{
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struct resource *resource;
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resource = new_resource(dev, index);
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resource->base = ((resource_t)basek) << 10;
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resource->size = ((resource_t)sizek) << 10;
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resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
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IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void pci_domain_read_resources(device_t dev)
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{
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struct resource *resource;
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/* Initialize the system wide io space constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
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resource->base = 0;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffUL;
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resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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/* Initialize the system wide memory resources constraints */
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resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
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resource->base = 0;
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resource->size = 0;
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resource->align = 0;
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resource->gran = 0;
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resource->limit = 0xffffffffUL;
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resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
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}
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static void tolm_test(void *gp, struct device *dev, struct resource *new)
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{
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struct resource **best_p = gp;
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struct resource *best;
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best = *best_p;
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if (!best || (best->base > new->base)) {
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best = new;
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}
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*best_p = best;
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}
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static u32 find_pci_tolm(struct bus *bus)
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{
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struct resource *min;
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u32 tolm;
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min = 0;
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search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
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tolm = 0xffffffffUL;
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if (min && tolm > min->base) {
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tolm = min->base;
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}
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return tolm;
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}
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static void pci_domain_set_resources(device_t dev)
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{
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device_t mc_dev;
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u32 pci_tolm;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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#if 1
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printk_debug("PCI mem marker = %x\n", pci_tolm);
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#endif
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/* FIXME Me temporary hack */
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if(pci_tolm > 0xe0000000)
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pci_tolm = 0xe0000000;
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/* Ensure pci_tolm is 128M aligned */
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pci_tolm &= 0xf8000000;
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mc_dev = dev->link[0].children;
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if (mc_dev) {
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/* Figure out which areas are/should be occupied by RAM.
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* This is all computed in kilobytes and converted to/from
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* the memory controller right at the edges.
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* Having different variables in different units is
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* too confusing to get right. Kilobytes are good up to
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* 4 Terabytes of RAM...
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*/
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u16 tolm_r, remapbase_r, remaplimit_r, remapoffset_r;
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u32 tomk, tolmk;
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u32 remapbasek, remaplimitk, remapoffsetk;
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/* Get the Top of Memory address, units are 128M */
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tomk = ((u32)pci_read_config16(mc_dev, TOM)) << 17;
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/* Compute the Top of Low Memory */
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tolmk = (pci_tolm & 0xf8000000) >> 10;
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if (tolmk >= tomk) {
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/* The PCI hole does not overlap memory
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* we won't use the remap window.
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*/
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tolmk = tomk;
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remapbasek = 0x3ff << 16;
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remaplimitk = 0 << 16;
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remapoffsetk = 0 << 16;
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}
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else {
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/* The PCI memory hole overlaps memory
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* setup the remap window.
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*/
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/* Find the bottom of the remap window
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* is it above 4G?
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*/
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remapbasek = 4*1024*1024;
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if (tomk > remapbasek) {
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remapbasek = tomk;
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}
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/* Find the limit of the remap window */
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remaplimitk = (remapbasek + (4*1024*1024 - tolmk) - (1 << 16));
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/* Find the offset of the remap window from tolm */
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remapoffsetk = remapbasek - tolmk;
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}
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/* Write the ram configruation registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(mc_dev, 0xc4);
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tolm_r = ((tolmk >> 17) << 11) | (tolm_r & 0x7ff);
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pci_write_config16(mc_dev, 0xc4, tolm_r);
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remapbase_r = pci_read_config16(mc_dev, 0xc6);
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remapbase_r = (remapbasek >> 16) | (remapbase_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc6, remapbase_r);
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remaplimit_r = pci_read_config16(mc_dev, 0xc8);
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remaplimit_r = (remaplimitk >> 16) | (remaplimit_r & 0xfc00);
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pci_write_config16(mc_dev, 0xc8, remaplimit_r);
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remapoffset_r = pci_read_config16(mc_dev, 0xca);
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remapoffset_r = (remapoffsetk >> 16) | (remapoffset_r & 0xfc00);
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pci_write_config16(mc_dev, 0xca, remapoffset_r);
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/* Report the memory regions */
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ram_resource(dev, 3, 0, 640);
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ram_resource(dev, 4, 768, (tolmk - 768));
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if (tomk > 4*1024*1024) {
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ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
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}
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if (remaplimitk >= remapbasek) {
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ram_resource(dev, 6, remapbasek,
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(remaplimitk + 64*1024) - remapbasek);
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}
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}
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assign_resources(&dev->link[0]);
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}
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static u32 pci_domain_scan_bus(device_t dev, u32 max)
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{
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max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
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if (max > max_bus) {
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max_bus = max;
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}
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return max;
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_childrens_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
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};
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static void mc_read_resources(device_t dev)
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{
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struct resource *resource;
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pci_dev_read_resources(dev);
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resource = new_resource(dev, 0xcf);
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resource->base = 0xe0000000;
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resource->size = max_bus * 4096*256;
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resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
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}
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static void mc_set_resources(device_t dev)
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{
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struct resource *resource, *last;
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last = &dev->resource[dev->resources];
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resource = find_resource(dev, 0xcf);
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if (resource) {
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report_resource_stored(dev, resource, "<mmconfig>");
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}
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pci_dev_set_resources(dev);
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}
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static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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{
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pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
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((device & 0xffff) << 16) | (vendor & 0xffff));
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}
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static struct pci_operations intel_pci_ops = {
|
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.set_subsystem = intel_set_subsystem,
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};
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static struct device_operations mc_ops = {
|
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.read_resources = mc_read_resources,
|
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.set_resources = mc_set_resources,
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.enable_resources = pci_dev_enable_resources,
|
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.init = 0,
|
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.scan_bus = 0,
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.ops_pci = &intel_pci_ops,
|
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};
|
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|
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static struct pci_driver mc_driver __pci_driver = {
|
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.ops = &mc_ops,
|
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.vendor = PCI_VENDOR_ID_INTEL,
|
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.device = PCI_DEVICE_ID_INTEL_3100_MC,
|
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};
|
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|
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static void cpu_bus_init(device_t dev)
|
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{
|
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initialize_cpus(&dev->link[0]);
|
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}
|
||||
|
||||
static void cpu_bus_noop(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_noop,
|
||||
.set_resources = cpu_bus_noop,
|
||||
.enable_resources = cpu_bus_noop,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
|
||||
static void enable_dev(device_t dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_intel_i3100_ops = {
|
||||
CHIP_NAME("Intel 3100 Northbridge")
|
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.enable_dev = enable_dev,
|
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};
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@ -0,0 +1,88 @@
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/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pciexp.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
#include <part/hard_reset.h>
|
||||
|
||||
typedef struct northbridge_intel_i3100_config config_t;
|
||||
|
||||
static void pcie_init(struct device *dev)
|
||||
{
|
||||
config_t *config;
|
||||
|
||||
/* Get the chip configuration */
|
||||
config = dev->chip_info;
|
||||
|
||||
if(config->intrline) {
|
||||
pci_write_config32(dev, 0x3c, config->intrline);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
|
||||
{
|
||||
u16 val;
|
||||
u16 ctl;
|
||||
int flag = 0;
|
||||
do {
|
||||
val = pci_read_config16(dev, 0x76);
|
||||
printk_debug("pcie porta 0x76: %02x\n", val);
|
||||
if ((val & (1<<10)) && (!flag)) { /* training error */
|
||||
ctl = pci_read_config16(dev, 0x74);
|
||||
pci_write_config16(dev, 0x74, (ctl | (1<<5)));
|
||||
val = pci_read_config16(dev, 0x76);
|
||||
printk_debug("pcie porta reset 0x76: %02x\n", val);
|
||||
flag=1;
|
||||
hard_reset();
|
||||
}
|
||||
} while (val & (3<<10));
|
||||
return pciexp_scan_bridge(dev, max);
|
||||
}
|
||||
|
||||
static struct device_operations pcie_ops = {
|
||||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pcie_init,
|
||||
.scan_bus = pcie_scan_bridge,
|
||||
.reset_bus = pci_bus_reset,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver pci_driver_0 __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA,
|
||||
};
|
||||
|
||||
static struct pci_driver pci_driver_1 __pci_driver = {
|
||||
.ops = &pcie_ops,
|
||||
.vendor = PCI_VENDOR_ID_INTEL,
|
||||
.device = PCI_DEVICE_ID_INTEL_3100_PCIE_PA1,
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,34 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Arastra, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
/* This code is based on src/northbridge/intel/e7520/raminit.h */
|
||||
|
||||
#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_H
|
||||
#define NORTHBRIDGE_INTEL_I3100_RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
u32 node_id;
|
||||
device_t f0, f1, f2, f3;
|
||||
u16 channel0[DIMM_SOCKETS];
|
||||
u16 channel1[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue