soc/amd/stoneyridge/lpc.c: Refactor lpc_enable_childrens_resources
Factor out the code into separate functions. Create set_lpc_resource that will set the resource for a particular child while lpc_enable_childrens_resources finds all children and calls set_lpc_resource for each child found. This creates well defined boundaries for each function. Change-Id: I265cfac2049733481faf8a6e5b02e34aadae11f5 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Richard Spiegel
Martin Roth
parent
1a81a4d135
commit
aa1838577d
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@ -152,69 +152,28 @@ static void lpc_set_resources(struct device *dev)
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pci_dev_set_resources(dev);
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whose children's resources are to be enabled
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*
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*/
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static void lpc_enable_childrens_resources(device_t dev)
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static void set_lpc_resource(device_t child,
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int *variable_num,
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u16 *reg_var,
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u32 *reg,
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u32 *reg_x,
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u16 reg_size,
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u8 *wiosize)
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{
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struct bus *link;
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u32 reg, reg_x;
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int var_num = 0;
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u16 reg_var[3];
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u16 reg_size[1] = {512};
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u8 wiosize = pci_read_config8(dev, 0x74);
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/* Be a bit relaxed, tolerate that LPC region might be bigger than
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* resource we try to fit, do it like this for all regions < 16 bytes.
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* If there is a resource > 16 bytes it must be 512 bytes to be able
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* to allocate the fresh LPC window.
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*
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* AGESA likes to enable already one LPC region in wide port base
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* 0x64-0x65, using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size
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* The code tries to check if resource can fit into this region.
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*/
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reg = pci_read_config32(dev, 0x44);
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reg_x = pci_read_config32(dev, 0x48);
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/* check if ranges are free and don't use them if already taken */
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if (reg_x & (1 << 2))
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var_num = 1;
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/* just in case check if someone did not manually set other ranges */
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if (reg_x & (1 << 24))
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var_num = 2;
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if (reg_x & (1 << 25))
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var_num = 3;
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/* check AGESA region size */
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if (wiosize & (1 << 0))
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reg_size[0] = 16;
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reg_var[2] = pci_read_config16(dev, 0x90);
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reg_var[1] = pci_read_config16(dev, 0x66);
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reg_var[0] = pci_read_config16(dev, 0x64);
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/* todo: clean up the code style here */
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for (link = dev->link_list ; link ; link = link->next) {
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device_t child;
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for (child = link->children; child;
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child = child->sibling) {
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if (child->enabled
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&& (child->path.type == DEVICE_PATH_PNP)) {
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struct resource *res;
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u32 base, end;
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u32 rsize = 0, set = 0, set_x = 0;
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u16 var_num;
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var_num = *variable_num;
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for (res = child->resource_list; res; res = res->next) {
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u32 base, end; /* don't need long long */
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u32 rsize, set = 0, set_x = 0;
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if (!(res->flags & IORESOURCE_IO))
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continue;
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base = res->base;
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end = resource_end(res);
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/* find a resource size */
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printk(BIOS_DEBUG, "Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n",
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printk(BIOS_DEBUG,
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"Southbridge LPC decode:%s, base=0x%08x, end=0x%08x\n",
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dev_path(child), base, end);
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switch (base) {
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case 0x60: /* KB */
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@ -283,41 +242,105 @@ static void lpc_enable_childrens_resources(device_t dev)
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rsize = 0;
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/* try AGESA allocated region in region 0 */
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if ((var_num > 0) && ((base >= reg_var[0]) &&
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((base + res->size) <= (reg_var[0] + reg_size[0]))))
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rsize = reg_size[0];
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((base + res->size) <= (reg_var[0] + reg_size))))
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rsize = reg_size;
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}
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/* check if region found and matches the enable */
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if (res->size <= rsize) {
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reg |= set;
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reg_x |= set_x;
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*reg |= set;
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*reg_x |= set_x;
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/* check if we can fit resource in variable range */
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} else if ((var_num < 3) &&
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((res->size <= 16) || (res->size == 512))) {
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} else if ((var_num < 3) && ((res->size <= 16) ||
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(res->size == 512))) {
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/* use variable ranges if pre-defined do not match */
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switch (var_num) {
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case 0:
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reg_x |= (1 << 2);
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*reg_x |= (1 << 2);
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if (res->size <= 16)
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wiosize |= (1 << 0);
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*wiosize |= (1 << 0);
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break;
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case 1:
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reg_x |= (1 << 24);
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*reg_x |= (1 << 24);
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if (res->size <= 16)
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wiosize |= (1 << 2);
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*wiosize |= (1 << 2);
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break;
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case 2:
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reg_x |= (1 << 25);
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*reg_x |= (1 << 25);
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if (res->size <= 16)
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wiosize |= (1 << 3);
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*wiosize |= (1 << 3);
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break;
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}
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reg_var[var_num++] =
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base & 0xffff;
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} else {
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printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n",
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printk(BIOS_ERR, "cannot fit LPC decode region:");
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printk(BIOS_ERR, "%s, base = 0x%08x, end = 0x%08x\n",
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dev_path(child), base, end);
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}
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}
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*variable_num = var_num;
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}
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/**
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* @brief Enable resources for children devices
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*
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* @param dev the device whose children's resources are to be enabled
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*
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*/
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static void lpc_enable_childrens_resources(device_t dev)
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{
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struct bus *link;
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u32 reg, reg_x;
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int var_num = 0;
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u16 reg_var[3];
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u16 reg_size[1] = {512};
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u8 wiosize = pci_read_config8(dev, 0x74);
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/* Be a bit relaxed, tolerate that LPC region might be bigger than
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* resource we try to fit, do it like this for all regions < 16 bytes.
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* If there is a resource > 16 bytes it must be 512 bytes to be able
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* to allocate the fresh LPC window.
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*
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* AGESA likes to enable already one LPC region in wide port base
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* 0x64-0x65, using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size
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* The code tries to check if resource can fit into this region.
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*/
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reg = pci_read_config32(dev, 0x44);
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reg_x = pci_read_config32(dev, 0x48);
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/* check if ranges are free and don't use them if already taken */
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if (reg_x & (1 << 2))
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var_num = 1;
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/* just in case check if someone did not manually set other ranges */
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if (reg_x & (1 << 24))
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var_num = 2;
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if (reg_x & (1 << 25))
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var_num = 3;
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/* check AGESA region size */
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if (wiosize & (1 << 0))
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reg_size[0] = 16;
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reg_var[2] = pci_read_config16(dev, 0x90);
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reg_var[1] = pci_read_config16(dev, 0x66);
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reg_var[0] = pci_read_config16(dev, 0x64);
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/* todo: clean up the code style here */
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for (link = dev->link_list; link; link = link->next) {
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device_t child;
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for (child = link->children; child;
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child = child->sibling) {
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if (child->enabled
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&& (child->path.type == DEVICE_PATH_PNP)) {
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set_lpc_resource(child,
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&var_num,
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reg_var,
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®,
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®_x,
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reg_size[0],
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&wiosize);
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}
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}
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}
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