Delete a file no longer used by the SiS implementation
No functional code changes. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Jordan Crouse <jordan.crouse@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Jordan Crouse
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/*
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* This file is part of the LinuxBIOS project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* Turn off machine check triggers when reading
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* pci space where there are no devices.
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* This is necessary when scaning the bus for
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* devices which is done by the kernel
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*
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* written in 2003 by Eric Biederman
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*
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* - Athlon64 workarounds by Stefan Reinauer
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* - "reset once" logic by Yinghai Lu
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* Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
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* Written by Morgan Tsai <my_tsai@sis.com> for SiS.
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*
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <part/hard_reset.h>
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#include <pc80/mc146818rtc.h>
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#include <bitops.h>
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#include <cpu/amd/model_fxx_rev.h>
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//#include "amdk8.h"
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#include <arch/io.h>
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/**
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* @brief Read resources for AGP aperture
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*
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* @param
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*
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* There is only one AGP aperture resource needed. The resoruce is added to
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* the northbridge of BSP.
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*
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* The same trick can be used to augment legacy VGA resources which can
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* be detect by generic pci reousrce allocator for VGA devices.
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* BAD: it is more tricky than I think, the resource allocation code is
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* implemented in a way to NOT DOING legacy VGA resource allcation on
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* purpose :-(.
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*/
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typedef struct msr_struct
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{
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unsigned lo;
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unsigned hi;
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} msr_t;
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static inline msr_t rdmsr(unsigned index)
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{
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msr_t result;
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result.lo = 0;
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result.hi = 0;
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return result;
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}
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static void sisnb_read_resources(device_t dev)
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{
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struct resource *resource;
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unsigned char iommu;
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/* Read the generic PCI resources */
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printk_debug("sisnb_read_resources\n");
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pci_dev_read_resources(dev);
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/* If we are not the first processor don't allocate the gart apeture */
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if (dev->path.u.pci.devfn != PCI_DEVFN(0x0, 0)) {
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return;
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}
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return;
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iommu = 1;
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get_option(&iommu, "iommu");
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if (iommu) {
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/* Add a Gart apeture resource */
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resource = new_resource(dev, 0x94);
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resource->size = iommu?AGP_APERTURE_SIZE:1;
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resource->align = log2(resource->size);
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resource->gran = log2(resource->size);
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resource->limit = 0xffffffff; /* 4G */
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resource->flags = IORESOURCE_MEM;
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}
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}
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static void set_agp_aperture(device_t dev)
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{
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struct resource *resource;
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return;
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resource = probe_resource(dev, 0x94);
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if (resource) {
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device_t pdev;
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uint32_t gart_base, gart_acr;
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/* Remember this resource has been stored */
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resource->flags |= IORESOURCE_STORED;
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/* Find the size of the GART aperture */
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gart_acr = (0<<6)|(0<<5)|(0<<4)|((resource->gran - 25) << 1)|(0<<0);
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/* Get the base address */
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gart_base = ((resource->base) >> 25) & 0x00007fff;
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/* Update the other northbriges */
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pdev = 0;
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while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1103, pdev))) {
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/* Store the GART size but don't enable it */
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pci_write_config32(pdev, 0x90, gart_acr);
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/* Store the GART base address */
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pci_write_config32(pdev, 0x94, gart_base);
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/* Don't set the GART Table base address */
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pci_write_config32(pdev, 0x98, 0);
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/* Report the resource has been stored... */
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report_resource_stored(pdev, resource, " <gart>");
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}
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}
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}
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static void sisnb_set_resources(device_t dev)
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{
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printk_debug("sisnb_set_resources ------->\n");
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/* Set the gart apeture */
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// set_agp_aperture(dev);
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/* Set the generic PCI resources */
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pci_dev_set_resources(dev);
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printk_debug("sisnb_set_resources <-------\n");
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}
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static void sisnb_init(struct device *dev)
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{
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uint32_t cmd, cmd_ref;
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int needs_reset;
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struct device *f0_dev, *f2_dev;
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msr_t msr;
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needs_reset = 0;
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printk_debug("sisnb_init: ---------->\n");
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//dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS756), 0);
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msr = rdmsr(0xC001001A);
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pci_write_config16(dev, 0x8E, msr.lo >> 16); // Topbound
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pci_write_config8(dev, 0x7F, 0x08); // ACPI Base
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outb(inb(0x856) | 0x40, 0x856); // Auto-Reset Function
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printk_debug("sisnb_init: <----------\n");
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printk_debug("done.\n");
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}
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static struct device_operations sisnb_ops = {
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.read_resources = sisnb_read_resources,
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.set_resources = sisnb_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sisnb_init,
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.scan_bus = 0,
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.ops_pci = 0,
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};
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static const struct pci_driver sisnb_driver __pci_driver = {
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.ops = &sisnb_ops,
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.vendor = PCI_VENDOR_ID_SIS,
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.device = PCI_DEVICE_ID_SIS_SIS761,
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};
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