From aa30d6237e0b55cbf15e5312ad68efdfbdc85642 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 15 Jan 2020 14:40:14 +0100 Subject: [PATCH] nb/intel/sandybridge: sort LANEBASE_* defines by their address Change-Id: I32fcd36298f41d3b6d8b3e16b6641b9404220461 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38437 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/sandybridge.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index ef1df061d6..f5c1e415c7 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -139,11 +139,11 @@ enum platform_type { #define LANEBASE_B1 0x0200 #define LANEBASE_B2 0x0400 #define LANEBASE_B3 0x0600 +#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ #define LANEBASE_B4 0x1000 #define LANEBASE_B5 0x1200 #define LANEBASE_B6 0x1400 #define LANEBASE_B7 0x1600 -#define LANEBASE_ECC 0x0800 /* ECC lane is in the middle of the data lanes */ /* byte lane register offsets */ #define GDCRTRAININGRESULT(ch, y) GzLy(0x0004, ch, y) /* Test results for PI config */