inteltool: add `-s` to dump spi bar and bios_cntl registers
Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: http://review.coreboot.org/8049 Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Alexander Couzens
Idwer Vollering
parent
9739846469
commit
aa3dd5d5db
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@ -27,7 +27,7 @@ PREFIX ?= /usr/local
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CFLAGS ?= -O2 -g -Wall -W
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LDFLAGS += -lpci -lz
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OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o
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OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o spi.o
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OS_ARCH = $(shell uname)
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ifeq ($(OS_ARCH), Darwin)
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@ -29,6 +29,9 @@ Dump I/O Controller Hub (ICH) southbridge GPIO registers.
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.B "\-r, \-\-rcba"
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Dump I/O Controller Hub (ICH) southbridge RCBA registers.
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.TP
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.B "\-s, \-\-spi"
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Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control.
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.TP
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.B "\-p, \-\-pmbase"
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Dump I/O Controller Hub (ICH) southbridge PMBASE registers.
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.TP
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@ -209,10 +209,11 @@ void print_version(void)
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void print_usage(const char *name)
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{
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printf("usage: %s [-vh?gGrpmedPMa]\n", name);
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printf("usage: %s [-vh?gGrpmedPMas]\n", name);
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printf("\n"
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" -v | --version: print the version\n"
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" -h | --help: print this help\n\n"
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" -s | --spi: dump southbridge spi and bios_cntrl registers\n"
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" -g | --gpio: dump southbridge GPIO registers\n"
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" -G | --gpio-diffs: show GPIO differences from defaults\n"
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" -r | --rcba: dump southbridge RCBA registers\n"
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@ -240,6 +241,7 @@ int main(int argc, char *argv[])
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int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0;
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int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0;
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int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0;
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int dump_spi = 0;
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int show_gpio_diffs = 0;
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static struct option long_options[] = {
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@ -255,11 +257,12 @@ int main(int argc, char *argv[])
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{"pciexpress", 0, 0, 'P'},
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{"msrs", 0, 0, 'M'},
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{"ambs", 0, 0, 'A'},
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{"spi", 0, 0, 's'},
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{"all", 0, 0, 'a'},
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{0, 0, 0, 0}
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};
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while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA",
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while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAs",
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long_options, &option_index)) != EOF) {
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switch (opt) {
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case 'v':
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@ -304,10 +307,14 @@ int main(int argc, char *argv[])
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dump_pciexbar = 1;
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dump_coremsrs = 1;
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dump_ambs = 1;
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dump_spi = 1;
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break;
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case 'A':
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dump_ambs = 1;
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break;
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case 's':
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dump_spi = 1;
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break;
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case 'h':
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case '?':
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default:
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@ -454,6 +461,10 @@ int main(int argc, char *argv[])
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if (dump_ambs) {
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print_ambs(nb, pacc);
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}
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if (dump_spi) {
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print_spi(sb);
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}
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/* Clean up */
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pci_free_dev(nb);
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// pci_free_dev(sb); // TODO: glibc detected "double free or corruption"
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@ -203,4 +203,5 @@ int print_epbar(struct pci_dev *nb);
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int print_dmibar(struct pci_dev *nb);
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int print_pciexbar(struct pci_dev *nb);
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int print_ambs(struct pci_dev *nb, struct pci_access *pacc);
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int print_spi(struct pci_dev *sb);
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void ivybridge_dump_timings(void);
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@ -0,0 +1,219 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include "inteltool.h"
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static const io_register_t pch_bios_cntl_registers[] = {
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{ 0x0, 1, "BIOSWE - write enable" },
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{ 0x1, 1, "BLE - lock enable" },
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{ 0x2, 2, "SPI Read configuration" },
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{ 0x4, 1, "TopSwapStatus" },
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{ 0x5, 1, "SMM Bios Write Protect Disable" },
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{ 0x6, 2, "reserved" },
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};
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#define SPIBAR 0x3800
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static const io_register_t spi_bar_registers[] = {
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{ SPIBAR + 0x00, 4, "BFPR - BIOS Flash primary region" },
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{ SPIBAR + 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
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{ SPIBAR + 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
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{ SPIBAR + 0x08, 4, "FADDR - Flash Address" },
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{ SPIBAR + 0x0c, 4, "Reserved" },
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{ SPIBAR + 0x10, 4, "FDATA0" },
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/* 0x10 .. 0x4f are filled with data */
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{ SPIBAR + 0x50, 4, "FRACC - Flash Region Access Permissions" },
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{ SPIBAR + 0x54, 4, "Flash Region 0" },
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{ SPIBAR + 0x58, 4, "Flash Region 1" },
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{ SPIBAR + 0x5c, 4, "Flash Region 2" },
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{ SPIBAR + 0x60, 4, "Flash Region 3" },
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{ SPIBAR + 0x64, 4, "Flash Region 4" },
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{ SPIBAR + 0x74, 4, "FPR0 Flash Protected Range 0" },
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{ SPIBAR + 0x78, 4, "FPR0 Flash Protected Range 1" },
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{ SPIBAR + 0x7c, 4, "FPR0 Flash Protected Range 2" },
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{ SPIBAR + 0x80, 4, "FPR0 Flash Protected Range 3" },
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{ SPIBAR + 0x84, 4, "FPR0 Flash Protected Range 4" },
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{ SPIBAR + 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
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{ SPIBAR + 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
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{ SPIBAR + 0x94, 2, "PREOP - Prefix opcode Configuration" },
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{ SPIBAR + 0x96, 2, "OPTYPE - Opcode Type Configuration" },
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{ SPIBAR + 0x98, 8, "OPMENU - Opcode Menu Configuration" },
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{ SPIBAR + 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
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{ SPIBAR + 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
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{ SPIBAR + 0xb8, 4, "Reserved" },
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{ SPIBAR + 0xc0, 4, "AFC - Additional Flash Control" },
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{ SPIBAR + 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
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{ SPIBAR + 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
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{ SPIBAR + 0xd0, 4, "FPB - Flash Partition Boundary" },
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};
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int print_bioscntl(struct pci_dev *sb)
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{
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int i, size = 0;
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unsigned char bios_cntl = 0xff;
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const io_register_t *bios_cntl_register = NULL;
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printf("\n============= SPI / BIOS CNTL =============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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bios_cntl = pci_read_byte(sb, 0xdc);
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bios_cntl_register = pch_bios_cntl_registers;
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size = ARRAY_SIZE(pch_bios_cntl_registers);
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break;
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default:
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printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n");
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return 1;
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}
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printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl);
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if (bios_cntl_register) {
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for (i = 0; i < size; i++) {
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unsigned int val = bios_cntl >> bios_cntl_register[i].addr;
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val &= ((1 << bios_cntl_register[i].size) -1);
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printf("0x%04x = %s\n", val, bios_cntl_register[i].name);
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}
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}
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return 0;
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}
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int print_spibar(struct pci_dev *sb) {
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int i, size = 0, rcba_size = 0x4000;
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volatile uint8_t *rcba;
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uint32_t rcba_phys;
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const io_register_t *spi_register = NULL;
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printf("\n============= SPI Bar ==============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH6:
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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case PCI_DEVICE_ID_INTEL_ICH8:
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH9DH:
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case PCI_DEVICE_ID_INTEL_ICH9DO:
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case PCI_DEVICE_ID_INTEL_ICH9R:
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case PCI_DEVICE_ID_INTEL_ICH9:
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case PCI_DEVICE_ID_INTEL_ICH9M:
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case PCI_DEVICE_ID_INTEL_ICH9ME:
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case PCI_DEVICE_ID_INTEL_ICH10R:
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case PCI_DEVICE_ID_INTEL_NM10:
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case PCI_DEVICE_ID_INTEL_I63XX:
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case PCI_DEVICE_ID_INTEL_3400:
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case PCI_DEVICE_ID_INTEL_3420:
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case PCI_DEVICE_ID_INTEL_3450:
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case PCI_DEVICE_ID_INTEL_3400_DESKTOP:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE:
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case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF:
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case PCI_DEVICE_ID_INTEL_B55_A:
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case PCI_DEVICE_ID_INTEL_B55_B:
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case PCI_DEVICE_ID_INTEL_H55:
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case PCI_DEVICE_ID_INTEL_H57:
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case PCI_DEVICE_ID_INTEL_HM55:
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case PCI_DEVICE_ID_INTEL_HM57:
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case PCI_DEVICE_ID_INTEL_P55:
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case PCI_DEVICE_ID_INTEL_PM55:
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case PCI_DEVICE_ID_INTEL_Q57:
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case PCI_DEVICE_ID_INTEL_QM57:
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case PCI_DEVICE_ID_INTEL_QS57:
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case PCI_DEVICE_ID_INTEL_Z68:
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case PCI_DEVICE_ID_INTEL_P67:
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case PCI_DEVICE_ID_INTEL_UM67:
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case PCI_DEVICE_ID_INTEL_HM65:
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case PCI_DEVICE_ID_INTEL_H67:
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case PCI_DEVICE_ID_INTEL_HM67:
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case PCI_DEVICE_ID_INTEL_Q65:
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case PCI_DEVICE_ID_INTEL_QS67:
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case PCI_DEVICE_ID_INTEL_Q67:
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case PCI_DEVICE_ID_INTEL_QM67:
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case PCI_DEVICE_ID_INTEL_B65:
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case PCI_DEVICE_ID_INTEL_C202:
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case PCI_DEVICE_ID_INTEL_C204:
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case PCI_DEVICE_ID_INTEL_C206:
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case PCI_DEVICE_ID_INTEL_H61:
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case PCI_DEVICE_ID_INTEL_Z77:
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case PCI_DEVICE_ID_INTEL_Z75:
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case PCI_DEVICE_ID_INTEL_Q77:
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case PCI_DEVICE_ID_INTEL_Q75:
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case PCI_DEVICE_ID_INTEL_B75:
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case PCI_DEVICE_ID_INTEL_H77:
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case PCI_DEVICE_ID_INTEL_C216:
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case PCI_DEVICE_ID_INTEL_QM77:
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case PCI_DEVICE_ID_INTEL_QS77:
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case PCI_DEVICE_ID_INTEL_HM77:
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case PCI_DEVICE_ID_INTEL_UM77:
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case PCI_DEVICE_ID_INTEL_HM76:
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case PCI_DEVICE_ID_INTEL_HM75:
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case PCI_DEVICE_ID_INTEL_HM70:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH:
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case PCI_DEVICE_ID_INTEL_ICH0:
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case PCI_DEVICE_ID_INTEL_ICH2:
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case PCI_DEVICE_ID_INTEL_ICH4:
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case PCI_DEVICE_ID_INTEL_ICH4M:
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case PCI_DEVICE_ID_INTEL_ICH5:
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printf("This southbridge does not have RCBA.\n");
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return 1;
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default:
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printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n");
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return 1;
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}
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rcba = map_physical(rcba_phys, rcba_size);
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if (rcba == NULL) {
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perror("Error mapping RCBA");
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exit(1);
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}
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for (i = 0; i < size; i++) {
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switch(spi_register[i].size) {
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case 1:
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printf("0x%08x = %s\n", *(uint8_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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break;
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case 2:
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printf("0x%08x = %s\n", *(uint16_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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break;
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case 4:
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printf("0x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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break;
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case 8:
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printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name);
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break;
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}
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}
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unmap_physical((void *)rcba, rcba_size);
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return 0;
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}
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int print_spi(struct pci_dev *sb) {
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return (print_bioscntl(sb) || print_spibar(sb));
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}
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